Elbrus architecture

Overview

Elbrus 2000 (Elbrus or e2k for short), is a SPARC-inspired VLIW architecture developed by the Moscow Center for SPARC Technology (MCST).

Elbrus machine code is organized into very long instruction words (VLIW), which consist of multiple so-called syllables that are executed together.

References

Several useful documents about Elbrus are available on the internet, albeit mostly in Russian.

• Руководство по эффективному программированию на платформе «Эльбрус» (elbrus-prog)
• Микропроцессоры и вычислительные комплексы семейства «Эльбрус»
• A series of articles about porting Embox to Elbrus: introduction, part 1, part 2, part 3
• Pictures of various Elbrus mainboards

Memory organization

Most operations in Elbrus code either:

• Take the values of one or more registers, compute a function, and write the result to another register, or
• Load a value from memory into a register or store a value from a register into memory.

Register file, RF (Регистровый файл , РгФ)

The 256 general-purpose registers of the Register File (RF/РгФ) are divided into two categories:

• 224 registers are part of the procedure stack in a windowed way. They can become available or unavailable during procedure calls and returns. (See also elbrus-prog chapter 9.3.1.1)
• 32 registers are global registers. They are available during the whole runtime of a program.

TODO: last eight global registers are designated rotatable area

Changing the register window

The procedure stack contains parameters and local data of procedures. Its top area is stored in the register file (RF). On overflow or underflow of the register file, its contents are automatically swapped in/out of memory. Launch of a new procedure allocates a window on the procedure stack, which may overlap with the calling procedure's window.

Procedure chain stack (стек связующей информации)

Stack of return addresses. It can only be manipulated by the operating system and the hardware. Its top area is stored in CF (chain file) registers.

On this stack the following information is encoded in two quad words:

• return address
• compilation unit index descriptor (CUIR)
• window base (wbs) in the register file
• presence of real 80 (?)
• predicate file
• user stack descriptor
• rotatable area base
• processor status register

On overflow or underflow of the chain file, its contents are automatically swapped in/out of memory.

Predicate file, PF (Предикатный файл, ПФ)

Comparison operations produce one-bit results (true or false) that can be stored in the predicate registers.

Predicates can be used in conditional control transfers (jumps/calls), or in the conditional execution of individual operations.

There are 32 predicate registers in the predicate file, which appear as %pred0 to %pred31 in assembly code.

Special purpose registers

Special purpose registers can be read using the rrs and rrd operations, and writing using the rws and rwd operations.

Regular Instructions

Elbrus' wide instructions (широкая команда, ШК) are comprised of a header syllable and zero or more additional syllables. Wide instructions are 8 byte aligned and up to 16 words (64 bytes) long.

Syllables

The first syllable is the header syllable. It is always present. Presence of other syllables depend on the purpose of the command. Syllables occur in the following order:

• HS
• SS
• ALS0, ALS1, ALS2, ALS3, ALS4, ALS5
• CS0
• ALES2, ALES5
• CS1
• ALES0, ALES1, ALES3, ALES4
• AAS0, AAS1, AAS2, AAS3, AAS4, AAS5
• LTS3, LTS2, LTS1, LTS0
• PLS2, PLS1, PLS0
• CDS2, CDS1, CDS0

Syllable packing

Semi-syllables ALES and AAS are a half-word (2 bytes) long. All other syllables are one word (4 bytes) long.

Syllables SS, ALS* and CS0 occur as indicated in the header syllable in the order described above. They are packed, e.g. if header bits indicate presence of ALS0 and ALS2 but not SS nor ALS1, then the syllable ALS0 follows directly after HS and ALS2 follows directly after ALS0.

If presence of ALES2 or ALES5 is indicated, then a whole word is allocated for them, whether both are present or not. The first of both to be present occupies the more significant half of the word, the second is encoded in the less significant half. For example, when looking at the syllables as bytes, if ALES2 and ALES5 are present, then the first two bytes of the little endian word contain ALES5 and the last two bytes contain ALES2. If only ALES5 is present, the first two bytes are empty and the last two bytes contain ALES5.

CS1 may follow right after the previously described syllables.

ALES{0,1,3,4} and AAS* start at the word indicated by the "middle pointer" from the header syllable. Their ordering is the same as for ALES2 and ALES5 (high half first, low half second) but they are all packed. This means that any two syllables of ALES{0,1,3,4} and AAS{0,1} may share a word. ALES* may not share a word with AAS{2,3,4,5} because presence of the latter implies presence of AAS0 and/or AAS1. For example, if ALES0, ALES1, ALES4, AAS0 and AAS2 are indicated, then they are encoded as ALES1, ALES0, AAS0, ALES4, two bytes left empty, and finally AAS2.

LTS*, PLS* and CDS* are decoded starting from the end of the wide command. CDS* and PLS* are not indicated by individual flags but rather by their number. For example, there cannot be a PLS2 without a PLS0 and PLS1. LTS take any remaining words between the other syllables. For example, if after the AAS there are five words remaining in the wide command and two CDS and one PLS are indicated, then two words for LTS are left. They would be encoded as LTS1, LTS0, PLS0, CDS1, CDS0.

We do not know what happens if more syllables are indicated than there is space allocated or if syllables are encoded to overlap.

HS - Header syllable

SS - Stubs syllable

Stubs syllable format 1 - SF1

Stubs syllable format 2 - SF2

ct condition codes

The condition code in the stubs syllable controls under which conditions a control transfer operation is executed.

#LOOP_END and #NOT_LOOP_END are sometimes spelled as %LOOP_END and %NOT_LOOP_END.

ALS - Arithmetic-logical syllables

See chapter 'Arithmetic-logical operations' for more information on the operands.

ALES - Arithmetic-logical extension syllables

CS - Control syllables

CS0 and CS1 encode different operations.

set*

The set* operation sets several parameters related to register windows. Most bits are encoded in the CS0 syllable itself, but some are also read from the LTS0 syllable.

According to ldis, setwd is always performed, but settr, setbn, and setbp have to be enabled by setting the corrsponding bits in CS0.

wait

disp/ldisp/sdisp/return

The disp operation prepares a jump to a different location by using one of the control transfer preparation registers (ctpr1 to ctpr3).

For disp and ldisp, the offset is relative to the start of the current instruction, and in multiples of eight bytes. For example, in an instruction at 0x1000, with CS0=40000042, we get disp %ctpr1, 0x1210.

ldisp is only allowed with ctpr2.

For sdisp, the system call number is not shifted. CS0=6000001a is sdisp %ctpr1, 0x1a.

The return operation doesn't take an offset. The offset field should be zero in this case.

setmas (setting the memory address specifier)

Memory address specifiers control multiple aspects of load and store operations. Their 7-bit format is described elsewhere.

The MAS can be independently specified for load and store operations, in CS1:

Array Prefetch Instructions

Array prefetch instructions are run asynchronously on the array access unit. They are always 16 bytes long. To assemble array prefetch instructions, the mnemonic fapb is used. To call an array prefetch program, load its address with ldisp to %ctpr2 (no need to call or ct). Even though array prefetch instructions should only ever be called by ldisp and are not processed using the same facilities as regular instructions, they always seem to be terminated by a regular branch instruction. The maximum length of an array prefetch program is 32 instructions.

Arithmetic-logical operations

ALU operations are generally identified by several aspects:

• The opcode field in the ALS
• If a corrsponding ALES exists, the opcode2 field in the ALES
• Opcode extension, opcode extension 2, and cmp opcode extension, depending on the opcode
• The ALUs in which the operation can be performed. Sometimes the same opcode can mean different operations in different ALUs (numbered from 0 to 5)

The format of an arithmetic-logical operation (ALOPF) is determined by opcode, channel, and presence of an ALES. The presence and location of additional identifying criteria of an operation as well as operands depend on the ALOPF.

Other variations:

• Some operations require two ALS
• Some operations require a Memory Address Specifier (MAS) in CS1
• Some operations have predicates. Some operations require additional data from CDS.
• ALOPF1, ALOPF2, ALOPF3, ALOPF7, ALOPF8 require no ALES, all others seem to require an ALES.

Operands and other fields

src1 encoding

src2 encoding

src2 that are not status register numbers are encoded as follows:

Literal half-syllables are sign-extended on access. Thus, values 0-0x7fff and 0xffff8000-0xffffffff (-0x8000 to -1) can be encoded in a literal half-syllable.

src3 encoding

dst encoding

dst that are not predicate register numbers or status register numbers are encoded as follows:

opcode2 values

Arithmetic-logical operation formats (ALOPF)

Several operand formats are defined.

For the locations of operands where none is explicitly specified here, see table 'Operands and other fields'.

TODO: ALOPF5, ALOPF6, ALOPF7, ALOPF9, ALOPF10, ALOPF19

NOTE: ALOPF9 and ALOPF10 have a 16 bit opcode extension

List of operations

The following tables are grouped by opcode2 and sorted by opcode.

Short operations (without ALES)

EXT (opcode2 = 1)