View VCD file in the browser
GitHub
https://drom.io/vcd/?github=<user>/<repo>/<brunch>/<filename>.vcd
Icarus
- https://drom.io/vcd/?github=dpretet/vcd/master/test1.vcd
- https://drom.io/vcd/?github=ombhilare999/riscv-core/master/src/rv32_soc_TB.vcd
- https://drom.io/vcd/?github=b06902044/computer_architecture/main/CPU.vcd
Verilator
- https://drom.io/vcd/?github=wavedrom/vcd-samples/trunk/swerv1.vcd
- https://drom.io/vcd/?github=bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/master/post_compile_files/vlt_dump.vcd
GHDL
- https://drom.io/vcd/?github=AdoobII/idea_21s/main/vhdl/idea.vcd
- https://drom.io/vcd/?github=yne/vcd/master/plasma.vcd
- https://drom.io/vcd/?github=yne/vcd/master/sample.vcd
- https://drom.io/vcd/?github=charlycop/VLSI-1/master/EXEC/ALU/alu.vcd
- https://drom.io/vcd/?github=gaoqqt2n/CPU/master/SuperPipelineCPU/vcdfile/pcpu.vcd
VCS
- https://drom.io/vcd/?github=sathyapriyanka/APB_UVC_UVM/5401170f6c74453c83f24df06ce9228c198f6d20/Apb_slave_uvm_new.vcd
- https://drom.io/vcd/?github=Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd
- https://drom.io/vcd/?github=Akashay-Singla/RISC-V/main/2_way_Superscalar/datapath_log.vcd
- https://drom.io/vcd/?github=ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd
QuestaSim
- https://drom.io/vcd/?github=mr-gaurav/Sequence-Counter/main/test.vcd
- https://drom.io/vcd/?github=SparshAgarwal/Computer-Architecture/master/hw3/hw3_1/dump.vcd
ModelSim
- https://drom.io/vcd/?github=Mohammad-Heydariii/Digital-Systems-Lab-Course/main/Lab_project4/modelsim_files/clkdiv2n_tb.vcd
- https://drom.io/vcd/?github=sh619/Songyu_Huang-Chisel/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd
QUARTUS_VCD_EXPORT
SystemC
- https://drom.io/vcd/?github=jroslindo/Mips-Systemc/main/REGISTRADORES_32_bits/wave_registradores.vcd
- https://drom.io/vcd/?github=amrhas/PDRNoC/VCRouter/noctweak/Debug/wavform.vcd.vcd
Xcelium (xmsim)
- https://drom.io/vcd/?github=hwiiiii/RISCV64-Simple-CPU/main/sim/cpu.vcd
- https://drom.io/vcd/?github=avidan-efody/wave_rerunner/main/test/data/integrated.vcd
⛔
treadle
https://drom.io/vcd/?github=chipsalliance/treadle/master/src/test/resources/GCD.vcd
Aldec
- https://drom.io/vcd/?github=SVeilleux9/FPGA-GPIO-Extender/main/Firmware/aldec/SPI_Write/SPI_Write.vcd (tgcd: 31000)
Riviera-PRO
MyHDL
- https://drom.io/vcd/?github=aibtw/myHdl_Projects/main/SimpleMemory/Simple_Memory.vcd
- https://drom.io/vcd/?github=Abhishek010397/Programming-RISC-V/master/top.vcd
- https://drom.io/vcd/?github=DarthSkipper/myHDL_Sigmoid/master/out/testbench/sigmoid_tb.vcd
⛔
ncsim
xilinx_isim
- https://drom.io/vcd/?github=mukul54/qrs-peak-fpga/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd
- https://drom.io/vcd/?github=DanieleParravicini/regex_coprocessor/master/scripts/sim/test2x2_regex22_string1.vcd
- https://drom.io/vcd/?github=pabloec1729/Hashes-generator/master/RTL/velocidad/test.vcd
Vivado
- https://drom.io/vcd//?github=saharmalmir/Eth2Ser/master/UART2ETH.runs/impl_1/iladata.vcd
- https://drom.io/vcd/?github=BradMcDanel/multiplication-free-dnn/master/verilog/iladata.vcd
GTKWave Analyzer
- https://drom.io/vcd/?github=Asfagus/Network-Switch/main/perm_current.vcd (Late start. t0 > 0)
Gist
https://drom.io/vcd/?gist=<user>/<hash>/raw/<hash>/<filename>.vcd
Bitbucket
https://drom.io/vcd//?bitbucket=<user>/<repo>/raw/<hash>/<filename>.vcd
GitLab
Cross-Origin Request Blocked
https://drom.io/vcd//?gitlab=<user>/<repo>/<brunch>/<filename>.vcd
https://drom.io/vcd//?gitlab=drom/vcd-samples/raw/main/swerv1.vcd (Verilator)
Snippets
https://gitlab.com/-/snippets/2162111/raw/main/test1.vcd
WaveQL fetch support
Second query source is an url of signal list file.
https://drom.io/vcd//?<host>=<path>.vcd&<host>=<path>.waveql