myhdl_simple_uart

A very simple UART implementation in MyHDL

This projects implements a simple UART in MyHDL and generates the VHDL files. It has been tested in a DE2-115 board.

It's a - very - simple implementation, I've done it to learn a little bit more about MyHDL.

The project has four files:

• baudrate_gen.py - generates the baudrate
• serial_rx.py - recieves info from RX
• serial_tx.py - sends info to TX
• tb_serial.py - testbench file

Running the project

To run the test and generate the VHDL Files go the terminal and execute the command: py.test tb_serial.py

You can also edit the tb_serial file and just call the toVHDL instructions

Viewing the waveforms

A bench.vcd file can be generated if you use the TraceSignals function at tb_serial.py, in order to do that you have to comment the VHDL Generation.

You can also run it without py.test, just call the test_bench function directly