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Top 269 VHDL open source projects

Geany is a small and lightweight integrated development environment. It was developed to provide a small and fast IDE, which has only a few dependencies from other packages. Another goal was to be as independent as possible from a special Desktop Environment like KDE or GNOME. So it is using only the GTK+ toolkit and therefore you need only the GTK+ runtime libraries to run Geany.

✭ 2,154

c C++VHDL TeX fortran M4

2. Ctags

A maintained ctags implementation

✭ 4,768

c C++M4 emacs lisp shell VHDL developer-tools code-analysis code-completion ctags code-navigation code-summarization tagjumping code-reading

3. Hackrf

low cost software radio platform

✭ 4,286

c CMake python VHDL Makefile assembly shell radio hardware sdr hackrf rf

4. zynqberry-pxfmini-uav-vivado

Vivado proyect for zynqberry-pxfmini autopilot

✭ 18

c VHDL tcl

5. second order sigma delta DAC

A comparison of 1st and 2nd order sigma delta DAC for FPGA

✭ 20

VHDL Verilog c

6. zturn-stuff

Various files for the MYiR ZTurn Zynq 7010 board

✭ 71

HTML Verilog c Eagle VHDL tcl

7. rfsoc qpsk

PYNQ example of using the RFSoC as a QPSK transceiver.

✭ 42

VHDL tcl Verilog c HTML python sdr pynq pynq-hardware-overlay fpga-soc qpsk voila voila-dashboard

8. Open-GPGPU-FlexGrip-

FlexGripPlus: an open-source GPU model for reliability evaluation and micro architectural simulation

✭ 15

VHDL Stata Sass gpu microarchitecture simulation-model

9. ghdl-yosys-blink

Blink an LED on an FPGA in VHDL using ghdl, yosys and nextpnr

✭ 19

Makefile VHDL

10. simple-riscv

A simple three-stage RISC-V CPU

✭ 14

VHDL tcl shell assembly c Makefile Batchfile fpga vhdl risc-v

11. BebiChiken

No description, website, or topics provided.

✭ 12

VHDL Verilog c assembly shell go Makefile

12. osvb

Open Source Verification Bundle for VHDL and System Verilog

✭ 23

python VHDL shell c Dockerfile Makefile

13. FPGA-TX

FPGA based transmitter

✭ 67

Verilog Coq VHDL python

14. Dexter

Software and FPGA code and PCB for Dexter the robot

✭ 44

c VHDL

15. SNES MiSTer ulx3s

SNES for MiSTer

✭ 15

VHDL Verilog SystemVerilog Coq tcl c

16. GBA MiSTer

GBA for MiSTer

✭ 96

VHDL Verilog lua SystemVerilog tcl C#Batchfile

17. FP-V-GA-Text

A simple to use VHDL module to display text on VGA display.

✭ 28

VHDL PHP

18. conifer

Fast inference of Boosted Decision Trees in FPGAs

✭ 16

python VHDL C++tcl shell c machine-learning fpga low-latency boosted-decision-trees

19. fpga ip

OscillatorIMP ecosystem FPGA IP sources

✭ 13

VHDL tcl Makefile c python Verilog

20. Gauntlet FPGA

FPGA implementation of Atari's Gauntlet arcade game

✭ 71

VHDL Verilog SystemVerilog Batchfile tcl python

21. zju-course

ZJU 信安19 课程资料

✭ 13

c HTML VHDL tcl Verilog shell

22. psi common

Common elements for FPGA Design (FIFOs, RAMs, etc.)

✭ 13

VHDL tcl fpga

23. SmartVHDL

SublimeText Plugin for VHDL (highlight, autocompletion, navigation, ...)

✭ 12

python VHDL syntax-highlighting navigation vhdl tooltip hierarchy instantiation alignement

24. wasca

Sega Saturn multipurporse cartridge

✭ 40

c Verilog SystemVerilog VHDL assembly Makefile

25. intfftk

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

✭ 43

VHDL Verilog matlab fpga dsp vhdl verilog fast-fourier-transform xilinx fft vivado altera cooley-tukey-fft digital-signal-processing fast-convolutions radix-2 integer-arithmetic route-optimization

26. TMR

Triple Modular Redundancy

✭ 16

Verilog tcl VHDL c shell assembly

27. MiSTery

Atari ST/STe core for MiST

✭ 27

Verilog SystemVerilog VHDL Makefile atari-st

28. fpga puf

🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.

✭ 44

VHDL c Makefile security fpga authentication vhdl fingerprint key-generation puf neorv32

29. hd6309sbc

Hitachi HD6309 Singleboard Computer

✭ 21

VHDL assembly

30. SBusFPGA

Stuff to put a FPGA in a SBus system (SPARCstation)

✭ 26

python c Verilog VHDL forth rust

31. whirlyfly

Hardware RNG for Papilio One based on the original Whirlygig

✭ 20

VHDL

32. fos

FOS - FPGA Operating System

✭ 49

VHDL c Coq Jupyter Notebook SystemVerilog tcl

33. Sweet32-CPU

Sweet32 32bit MRISC CPU - VHDL and software toolchain sources (including documentation)

✭ 30

VHDL c assembly C++TeX HTML

34. PlayStation MiSTer

PlayStation for MiSTer FPGA

✭ 180

VHDL Verilog SystemVerilog tcl

35. rygar-fpga

A FPGA core for the arcade game, Rygar (1986).

✭ 17

VHDL Verilog SystemVerilog c Coq tcl game fpga arcade mister rygar

36. router

清华大学2019计网联合实验第一组

✭ 27

VHDL Coq V Verilog assembly SystemVerilog

37. Atari800 MiSTer

Atari 800XL/65XE/130XE for MiSTer

✭ 23

VHDL Verilog SystemVerilog c assembly tcl

38. bladeRF-adsb

bladeRF ADS-B hardware decoder

✭ 84

VHDL c matlab

39. DIPSY

No description, website, or topics provided.

✭ 22

C++pascal VHDL Verilog python

40. SpinalDoc

SpinalHDL documentation assets (pictures, slides, ...)

✭ 23

HTML TeX VHDL CSS

41. FPGA-OV7670-cam

VHDL/FPGA/OV7670

✭ 26

VHDL

42. FreePDK45-RRAM-Addon

A RRAM addon for the NCSU FreePDK 45nm

✭ 12

HTML VHDL python perl HCL Verilog

43. 1bitSDR

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

✭ 53

VHDL Verilog HTML c SystemVerilog V fpga ham-radio amateur-radio verilog sdr lattice lattice-machxo2

44. nanocounter

An FPGA/STM32 based frequency counter with an Android user interface

✭ 26

java C++VHDL c python assembly

45. videoconditioner

RGB video input for Altera DE1 board + PAL Modulator

✭ 21

KiCad Layout VHDL Verilog

46. MiSTer-Arcade-SEGASYS1

FPGA implementation of SEGA SYSTEM 1 arcade board

✭ 18

Verilog VHDL SystemVerilog Coq tcl Batchfile

47. libv

Useful set of library functions for VHDL

✭ 46

VHDL shell

48. Altera-Cyclone-IV-board-V3.0

Documentation for Chinese ALTERA Cyclone IV EP4CE6 FPGA Development Board

✭ 58

PureBasic c Verilog VHDL Makefile HTML

49. Sudoku-Solver

A brute force algorithm on hardware is used to solve a sudoku. When a valid fill is not found backtracking is done. Backtracking is repeated until last number is a valid guess i.e guess out of 1 to 9. Digital logic realised using priority encoders and multiplexers.

✭ 12

VHDL c

50. zx-sizif-512

ZX Spectrum CPLD-based clone for rubber case

✭ 92

KiCad Layout KiCad Schematic SystemVerilog Verilog VHDL assembly zxspectrum pcb z80 verilog zx-spectrum cpld divmmc

1-50 of 269 VHDL projects

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