riscv / Riscv Debug Spec
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Working Draft of the RISC-V Debug Specification Standard
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RISC-V Debug Specification
You may be looking for one of the following pre-built PDFs:
Build Instructions
sudo apt-get install git make python3 python3-sympy graphviz texlive-full
make
There are two other interesting make targets:
-
make debug_defines.h
creates a C header file containing constants for addresses and fields of all the registers and abstract commands. -
make chisel
creates scala files for DM registers and abstract commands with the same information.
Contributing
There are various ways to contribute to this spec. You can use a combination of them to get your idea across. Please note that pull requests will only be reviewed/accepted from RISC-V Foundation members.
- Make a PR. This is the best way to deal with minor typos and edits.
- File an issue with something that you want to know or see.
- Discuss higher-level questions or ideas on the riscv-debug-group mailing list: https://groups.google.com/a/groups.riscv.org/forum/#!forum/debug
For More Information
Additional information can be found at https://github.com/riscv/debug-taskgroup
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