kleverRead-only mirror of the Klever Git repository
Stars: ✭ 18 (-41.94%)
Mutual labels: formal-methods, formal-verification, formal-specification
acsl-provedFully proved small C functions (examples for verification course).
Stars: ✭ 14 (-54.84%)
Mutual labels: formal-verification, frama-c
high-assurance-legacyLegacy code connected to the high-assurance implementation of the Ouroboros protocol family
Stars: ✭ 81 (+161.29%)
Mutual labels: formal-methods, formal-verification
fm-notesUnassorted scribbles on formal methods, type theory, category theory, and so on, and so on
Stars: ✭ 19 (-38.71%)
Mutual labels: formal-methods, formal-verification
intrepidIntrepyd Model Checker
Stars: ✭ 14 (-54.84%)
Mutual labels: formal-methods, formal-verification
vsrl-frameworkThe Verifiably Safe Reinforcement Learning Framework
Stars: ✭ 42 (+35.48%)
Mutual labels: formal-methods, formal-verification
reasonml-tic-tac-toewww.imandra.ai
Stars: ✭ 19 (-38.71%)
Mutual labels: formal-methods, formal-verification
pldi19-equivalence-checkerSource code for the equivalence checker presented in the PLDI 2019 paper, "Semantic Program Alignment for Equivalence Checking"
Stars: ✭ 30 (-3.23%)
Mutual labels: formal-verification
lms-verifygenerative programming & verification
Stars: ✭ 29 (-6.45%)
Mutual labels: frama-c
awesome-rust-formalized-reasoningAn exhaustive list of all Rust resources regarding automated or semi-automated formalization efforts in any area, constructive mathematics, formal algorithms, and program verification.
Stars: ✭ 185 (+496.77%)
Mutual labels: formal-verification
tm-proposer-idrisFormalization of Tendermint proposer election properties
Stars: ✭ 15 (-51.61%)
Mutual labels: formal-verification
tlacliA script for running TLA+/TLC from the command line
Stars: ✭ 75 (+141.94%)
Mutual labels: formal-methods
formal hw verificationTrying to verify Verilog/VHDL designs with formal methods and tools
Stars: ✭ 32 (+3.23%)
Mutual labels: formal-verification
RiscvSpecFormalThe RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
Stars: ✭ 69 (+122.58%)
Mutual labels: formal-verification
FreeSpecA framework for implementing and certifying impure computations in Coq
Stars: ✭ 48 (+54.84%)
Mutual labels: formal-verification
tezedge-specificationTLA+ specs and models for the TezEdge node's p2p overlay network, shell, and consensus
Stars: ✭ 19 (-38.71%)
Mutual labels: formal-verification
TSNschedAutomated Schedule Generation for Time-Sensitive Networks (TSN).
Stars: ✭ 46 (+48.39%)
Mutual labels: formal-methods
suslikSynthesis of Heap-Manipulating Programs from Separation Logic
Stars: ✭ 107 (+245.16%)
Mutual labels: deductive-reasoning
TorXakisA tool for Model Based Testing
Stars: ✭ 40 (+29.03%)
Mutual labels: formal-methods
llvm-semanticsFormal semantics of LLVM IR in K
Stars: ✭ 42 (+35.48%)
Mutual labels: formal-methods
