vlsistuff

ideas and eda software for vlsi design moving to python3, some directories were renamed to to have suffix "3" to signify python3 versio. gradually removing python2 remains.

#genver macro preprossor on verilog files, to aid in writing long verilog structures.

#synlib turning liberty format files into what You need: simulation and more.

#vcd_python reading vcd files and making sense out of them (in Python)

#vcd_python_c reading vcd files and making sense out of them (engine in C) much faster

#python-verilog simulation with python driving and monitoring the simulation. replacement of SV-UVM ugly sisters. moving to python3. still need to update directions.

#pybin just copy of python scripts from all previous.

#waveformer write waveforms in a text file and get svg or png drawing.

#verification_libs python helpers for verification with python-verilog connection. logs.py helps with logging and data converts. there are apb axi ad other helpers.

#zDraw rewrite of zDraw using pygame (as openGL became obsolete on my MacBook).

MIT license