Cheap and reliable Node.js hosting starts at $3/month, and $1/month static HTML hosting

Created with love in Canada, visit hostnodejs.com today

Feel like to post an Ad? Learn Details

All Programming Languages → Verilog

Top 626 Verilog open source projects

Proxmark 3

✭ 2,374

c Stata C++lua Verilog Makefile

Rocket Chip Generator

✭ 2,079

scala C++python Verilog shell Makefile assembly rtl riscv rocket-chip chip-generator chisel

3. E200 opensource

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

✭ 1,909

Verilog c assembly C++scala Makefile verilog cpu china core risc-v nuclei ultra-low-power

Yosys Open SYnthesis Suite

✭ 1,992

C++Verilog TeX python SystemVerilog Yacc

PicoRV32 - A Size-Optimized RISC-V CPU

✭ 1,856

Verilog assembly c Makefile shell python

❤️中国科学技术大学课程资源

✭ 11,274

C++LLVM python tcl Verilog TeX computer-science course share ustc

John the Ripper jumbo - advanced offline password cracker, which supports hundreds of hash and cipher types, and runs on many operating systems, CPUs, GPUs, and even some FPGAs

✭ 5,656

c Verilog python perl assembly M4 gpu password fpga hash opencl simd gpgpu mpi openmp ripper cracker john jtr crypt

浙江大学课程攻略共享计划

✭ 23,886

HTML c C++Verilog assembly python

You like pytorch? You like micrograd? You love tinygrad! ❤️

✭ 5,113

python Verilog c Objective-C++shell C++

10. Rekcarc Tsc Uht

清华大学计算机系课程攻略 Guidance for courses in Department of Computer Science and Technology, Tsinghua University

✭ 20,401

HTML c C++Verilog java assembly computer-science course course-project tsinghua-university course-assignment

11. first-fpga-pcb

FPGA dev board based on Lattice iCE40 8k

✭ 45

Verilog Coq Makefile python

12. NAND-Flash-Memory-Controller-verification

No description, website, or topics provided.

✭ 22

SystemVerilog Verilog Makefile

CMod-S6 SoC

✭ 30

Verilog c C++assembly Makefile perl objective c fpga fpga-soc wishbone verilator zipcpu wishbone-bus

The Ynot Project source code.

✭ 18

Coq ocaml Verilog

15. caravel mpw-one

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

✭ 130

Verilog shell tcl Makefile python c magic yosys caravel picorv32 openroad openram sky130

16. FPGA lecture

Source Codes for a lecture entitled "Parallel and Reconfigurable VLSI Computing" in Tokyo Tech.

✭ 20

17. second order sigma delta DAC

A comparison of 1st and 2nd order sigma delta DAC for FPGA

✭ 20

D startup- and library-files for ARM Cortex-M Microcontrollers

✭ 12

Haskell library for hardware description

✭ 81

haskell Verilog shell fpga rtl verilog hardware-description

No description, website, or topics provided.

✭ 32

Verilog scala c C++python TeX

21. rc-fpga-zcu

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

✭ 34

tcl scala Verilog C++c SystemVerilog rocket-chip vivado risc-v linux-boot fpga-board zcu102 zynqmp

22. zturn-stuff

Various files for the MYiR ZTurn Zynq 7010 board

✭ 71

HTML Verilog c Eagle VHDL tcl

PYNQ example of using the RFSoC as a QPSK transceiver.

✭ 42

VHDL tcl Verilog c HTML python sdr pynq pynq-hardware-overlay fpga-soc qpsk voila voila-dashboard

ideas and eda software for vlsi design

✭ 23

python Verilog c C++HTML shell

No description, website, or topics provided.

✭ 17

C++Verilog c shell CMake python

Quasar 2.0: Chisel equivalent of SweRV-EL2

✭ 19

scala SystemVerilog perl c Verilog C++processor chisel riscv rtl chisel3 open-source-hardware verilator asic-verification axi4 ahb-lite asic-design swerv swerv-el2

Hardware generation library based on "Kernel IP" (KIP) cores: programmable execution kernels inferred from microarchitectural templates

✭ 12

assembly kotlin Stata c SystemVerilog Verilog

The CAT Board is a Raspberry Pi HAT with a Lattice iCE40HX FPGA.

✭ 53

Jupyter Notebook python Verilog shell

A basic Soft(Gate)ware Defined Radio architecture

✭ 34

Verilog C++Makefile OpenSCAD perl shell

FPGA based PDP-8/i clone in verilog. Includes several TSS/8 sources and utiltities to build from source

✭ 16

Verilog c Roff Module Management System HTML Makefile

31. NetFPGA-10G-UPB-OpenFlow

An OpenFlow implementation for the NetFPGA-10G card

✭ 15

Verilog C++c python Makefile Stata

An Open Source alternative to Oracle Tuxedo

✭ 15

C++c M4 Makefile Verilog shell middleware atmi tuxedo xatmi fml32

33. cocotbext-axi

AXI interface modules for Cocotb

✭ 59

python Makefile Verilog

No description, website, or topics provided.

✭ 12

VHDL Verilog c assembly shell go Makefile

35. SIMD-architecture

Overall multi-core SIMD microarchitecture

✭ 23

[HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4

✭ 22

c assembly Verilog

37. proxmark3-amiimicyou

Proxmark3 Amiibo simulator as shown at Recon Montreal 2018

✭ 51

c Stata C++lua Verilog Makefile

Opensat first generation cubesat bus, launch into orbit at 2016/11/11

✭ 22

c Verilog C++assembly python HTML satellite spacecraft telemetry sdr gnuradio

FPGA based transmitter

✭ 67

Verilog Coq VHDL python

Verilog实现的简单五级流水线CPU，开发平台：Nexys3

✭ 24

41. OV7670-Verilog

Verilog modules required to get the OV7670 camera working

✭ 38

42. SNES MiSTer ulx3s

SNES for MiSTer

✭ 15

VHDL Verilog SystemVerilog Coq tcl c

GBA for MiSTer

✭ 96

VHDL Verilog lua SystemVerilog tcl C#Batchfile

IDEA project source files

✭ 50

Verilog C++CMake python Makefile groovy logic-synthesis

45. systemctlm-cosim-demo

No description, website, or topics provided.

✭ 46

C++Makefile SystemVerilog Verilog c

CPU microarchitecture, step by step

✭ 140

Verilog shell Batchfile SystemVerilog tcl assembly

mantle library

✭ 35

Hardware generator debugger

✭ 23

C++python CMake Verilog SystemVerilog shell

49. schoolRISCV

CPU microarchitecture, step by step

✭ 53

Makefile Verilog assembly python SystemVerilog tcl

OscillatorIMP ecosystem FPGA IP sources

✭ 13

VHDL tcl Makefile c python Verilog

1-50 of 626 Verilog projects