language-agdaAgda language support for the Atom editor
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AgdaAgda is a dependently typed programming language / interactive theorem prover.
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agda-from-nothingA workshop on learning Agda with minimal prerequisites.
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agdaThe theory of algebraic graphs formalised in Agda
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cubical-1labA formalised, cross-linked reference resource for mathematics done in Homotopy Type Theory
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MtacARMtac in Agda
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cainCategory theory applied to functional programming (undergraduate project)
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dicyA builder for LaTeX, knitr, literate Agda, literate Haskell and Pweave that automatically builds dependencies.
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msla2014wherein I implement several substructural logics in Agda
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org-agda-modeAn Emacs mode for working with Agda code in an Org-mode like fashion, more or less.
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ConsHoTTConstructive Interpretations of HoTT
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agda-pkgapkg - package manager for Agda
Stars: ✭ 30 (+7.14%)
AutoInAgdaProof automation – for Agda, in Agda.
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tt-in-cubicalType Theory in Type Theory using Cubical Agda
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atacaA TACtic library for Agda
Stars: ✭ 47 (+67.86%)
agda-modeAccessing Agda's interaction mode via command line & external tactic for Agda.
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catA formalization of category theory in cubical Agda
Stars: ✭ 50 (+78.57%)
TypeTopologyLogical manifestations of topological concepts, and other things. This version adopts the univalent point of view.
Stars: ✭ 132 (+371.43%)
frp agdaFunctional Reactive Programming with Agda
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universe-of-syntaxA universe of scope- and type-safe syntaxes (syntices?). Includes generic implementation of type-preserving renaming/substitution with all the proofs you could possibly need.
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awesome-dvAwesome ASIC design verification
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vsrl-frameworkThe Verifiably Safe Reinforcement Learning Framework
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intrepidIntrepyd Model Checker
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libsparkcryptoA cryptographic library in SPARK 2014
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tutoriel wpFrama-C and WP tutorial
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FreeSpecA framework for implementing and certifying impure computations in Coq
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RiscvSpecFormalThe RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
Stars: ✭ 69 (+146.43%)
tezedge-specificationTLA+ specs and models for the TezEdge node's p2p overlay network, shell, and consensus
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avrReads a state transition system and performs property checking
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formal hw verificationTrying to verify Verilog/VHDL designs with formal methods and tools
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fm-notesUnassorted scribbles on formal methods, type theory, category theory, and so on, and so on
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high-assurance-legacyLegacy code connected to the high-assurance implementation of the Ouroboros protocol family
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gammaAn Eclipse-based modeling framework for the component-based design and analysis of reactive systems
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pldi19-equivalence-checkerSource code for the equivalence checker presented in the PLDI 2019 paper, "Semantic Program Alignment for Equivalence Checking"
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awesome-rust-formalized-reasoningAn exhaustive list of all Rust resources regarding automated or semi-automated formalization efforts in any area, constructive mathematics, formal algorithms, and program verification.
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acsl-provedFully proved small C functions (examples for verification course).
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tm-proposer-idrisFormalization of Tendermint proposer election properties
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kleverRead-only mirror of the Klever Git repository
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