3 open source projects by bluespec

RISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT