Project ZiplineDefines a lossless compressed data format that is independent of CPU type, operating system, file system, and character set, and is suitable for compression using the XP10 algorithm.
SpispyAn open source SPI flash emulator and monitor
ZetOpen source implementation of a x86 processor
Fpusynthesiseable ieee 754 floating point library in verilog
OpentimerA High-performance Timing Analysis Tool for VLSI Systems
FluteRISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
LitepcieSmall footprint and configurable PCIe core
Biriscv32-bit Superscalar RISC-V CPU
Fpga nesFPGA-based Nintendo Entertainment System Emulator
PiccoloRISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
RidecoreRIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.
Basejump stlBaseJump STL: A Standard Template Library for SystemVerilog
Wb2axipBus bridges and other odds and ends
FpgaThe USRP™ Hardware Driver FPGA Repository
AccdnnA compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
KestrelThe Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.
Verilog I2cVerilog I2C interface for FPGA implementation
PoprcA Compiler for the Popr Language
Sv ParserSystemVerilog parser library fully complient with IEEE 1800-2017
MetroboyMetroBoy - A playable, circuit-level simulation of an entire Game Boy
Cnn Fpga使用Verilog实现的CNN模块,可以方便的在FPGA项目中使用
Sha256Hardware implementation of the SHA-256 cryptographic hash function
Fpg1PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.
DegateOpen source software for chip reverse engineering.
TinytpuImplementation of a Tensor Processing Unit for embedded systems and the IoT.
Sv2vSystemVerilog to Verilog conversion
Learning Nvdla NotesNVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]
LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
SlangSystemVerilog compiler and language services
Ice40 PlaygroundVarious iCE40 cores / projects to play around with (mostly targeted at the icebreaker)
Chisel3Chisel 3: A Modern Hardware Design Language
SimplevoutA Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals
Openwifiopen-source IEEE 802.11 WiFi baseband FPGA (chip) design
IcesugariCESugar FPGA Board (base on iCE40UP5k)
OpenfpgaduinoAll open source file and project for OpenFPGAduino project
E200 opensourceThis repository hosts the project for open-source hummingbird E203 RISC processor Core.
Symbiflow Arch DefsFOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
OpenofdmSythesizable, modular Verilog implementation of 802.11 OFDM decoder.
Wbuart32A simple, basic, formally verified UART controller
AesVerilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.
Fpga based cnnFPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.
NandlandAll code found on nandland is here. underconstruction.gif
MilkymistSoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU