screen-pong

The project.

Screen-pong is a remake in HDL of the famous Atari game for FPGA and VGA monitors.

The stages.

The project has undergone many changes since it began. Several versions or stages can be distinguished in it. That for historical reasons are kept in the project although separated in different subdirectories.

• In the first version (stage-01) of this game, a monolithic video controller (640x480@72Hz) programmed in an iceZum Alhambra. To develop the game, the icestudio tool was used for the blocks and their structure, together with code written directly in Verilog files. The strategy here was to feed the color pixel in a feedback loop on the same VGA controller. This version was quickly limited by the processing speed of the controller block and the capacity (1K) of the iceZum Alhambra. Is for this that version does not have a scoreboard for goals.

• In a second version (stage-02) we used the iPxs structure that Sergio Cuenca developed as a collection of icestudio named collection-iPxs. This was a more linear structure that simplifies the generation of VGA video in an FPGA. The use of the icestudio tool was made more intensive and the TinyFPGA-B2 was used to test the complete game. In this second version, a set of examples and blocks packaged in the form of a icestudio's collection is created that allows to show the development of the game as a tutorial. It also allows you to reuse blocks to create other types of games. You can find the collection for icestudio on github, in a separate repository call collection-Pong.

• In a third version (stage-03), different ways are used to describe the same game circuit, all of them separated into different subdirectories:

  • In icestudio the entire design is compacted in a single file in ICE format.
  • In verilog, all the files necessary to become independent from icestudio are generated. It includes a test to simulate using Verilator.
  • In nMigen the design is generated using Python.
  • In VHDL all Verilog files are, step by step, transformed to VHDL code.

  In this third stage or version of the project, the TinyFPG-BX is used for the synthesis.

The future.

It is desired in the future to be able to reuse and group the existing code and make it independent of the board that is used to synthesize.

Install and testing the project.

To install and test each of the versions, read and follow the installation instructions in each of the README.md files in the different directories.