All Git Users → alexforencich

12 open source projects by alexforencich

[ Open user page on Github ]

1. Verilog Uart

Verilog UART

✭ 174

verilog

2. Verilog I2c

Verilog I2C interface for FPGA implementation

✭ 171

verilog

3. Verilog Ethernet

Verilog Ethernet components for FPGA implementation

✭ 699

verilog

4. Verilog Axi

Verilog AXI components for FPGA implementation

✭ 349

verilog

5. Verilog Axis

Verilog AXI stream components for FPGA implementation

✭ 260

python

6. Verilog Pcie

Verilog PCI express components

✭ 252

verilog

7. cocotbext-axi

AXI interface modules for Cocotb

✭ 59

python Makefile Verilog

8. verilog-wishbone

Verilog wishbone components

✭ 67

python Verilog

9. verilog-lfsr

Fully parametrizable combinatorial parallel LFSR/CRC module

✭ 84

Verilog python

10. xfcp

Extensible FPGA control platform

✭ 39

Verilog python Makefile tcl shell

11. ftjrev

JTAG reverse engineering software for FTDI compatible cables

✭ 38

c python

12. cocotbext-eth

Ethernet interface modules for Cocotb

✭ 27

python Makefile Verilog

1-12 of 12 user projects