AmeerAbdelhadi / Indirectly Indexed 2d Ternary Content Addressable Memory Tcam
Licence: other
Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)
Labels
Projects that are alternatives of or similar to Indirectly Indexed 2d Ternary Content Addressable Memory Tcam
Fftdemo
A demonstration showing how several components can be compsed to build a simulated spectrogram
Stars: ✭ 23 (+155.56%)
Mutual labels: verilog
Netlist Graph
Java library for parsing and manipulating graph representations of gate-level Verilog netlists
Stars: ✭ 7 (-22.22%)
Mutual labels: verilog
Upduino Ov7670 Camera
Design to connect Lattice Ultraplus FPGA to OV7670 Camera Module
Stars: ✭ 17 (+88.89%)
Mutual labels: verilog
Amiga2000 Gfxcard
MNT VA2000, an Open Source Amiga 2/3/4000 Graphics Card (Zorro II/III), written in Verilog
Stars: ✭ 942 (+10366.67%)
Mutual labels: verilog
Naivecpu
A CPU that implementing THCO-MIPS16 instruction set.
Stars: ✭ 5 (-44.44%)
Mutual labels: verilog
Busblaster
KT-Link compatible buffer for the Bus Blaster v3
Stars: ✭ 6 (-33.33%)
Mutual labels: verilog
Lenet accelerator
A Lenet ASIC Accelerator targeting minimum number of cycles
Stars: ✭ 17 (+88.89%)
Mutual labels: verilog
Co4618
This repo is for the 4618 group nember to share code.
Stars: ✭ 5 (-44.44%)
Mutual labels: verilog
Aoocs
The OpenCores aoOCS SoC is a Wishbone compatible implementation of most of the Amiga Original Chip Set (OCS) and computer functionality. aoOCS is not related in any way with Minimig - it is a new and independent Amiga OCS implementation.
Stars: ✭ 23 (+155.56%)
Mutual labels: verilog
Cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Stars: ✭ 740 (+8122.22%)
Mutual labels: verilog
Verilog Vga Controller
A very simple VGA controller written in verilog
Stars: ✭ 16 (+77.78%)
Mutual labels: verilog
Novena Afe Hs Fpga
High Speed Analog Front End FPGA Firmware for Novena PVT1
Stars: ✭ 8 (-11.11%)
Mutual labels: verilog
Ocpi
Semi-private RTL development upstream of OpenCPI - this is *not* the OpenCPI repo!
Stars: ✭ 24 (+166.67%)
Mutual labels: verilog
Modular SRAM-based Indirectly-indexed
Ternary Content Addressable Memory IITCAM
Ameer M. S. Abdelhadi and Guy G. F. Lemieux
The University of British Columbia (UBC) 2016
{ ameer.abdelhadi; guy.lemieux } @ gmail.com
A fully parameterized and generic Verilog implementation of the suggested modular SRAM-based indirectly-indexed hierarchical-search TCAM (IITCAM), together with other approaches are provided as open source hardware. A run-in-batch flow manager to simulate and synthesize different designs with various parameters in batch using Altera's ModelSim and Quartus is also provided.
LICENSE: BSD 3-Clause ("BSD New" or "BSD Simplified") license.
Note that the project description data, including the texts, logos, images, and/or trademarks,
for each open source project belongs to its rightful owner.
If you wish to add or remove any projects, please contact us at [email protected].