FletcherFletcher: A framework to integrate FPGA accelerators with Apache Arrow
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UvvmUVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
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Awesome Model QuantizationA list of papers, docs, codes about model quantization. This repo is aimed to provide the info for model quantization research, we are continuously improving the project. Welcome to PR the works (papers, repositories) that are missed by the repo.
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OrcaRISC-V by VectorBlox
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PotatoA simple RISC-V processor for use in FPGA designs.
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SpinalDevDocker Development Environment for SpinalHDL
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