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intfftkFully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
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Image ProcessingImage Processing Toolbox in Verilog using Basys3 FPGA
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xedaCross EDA Abstraction and Automation
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Clash CompilerHaskell to VHDL/Verilog/SystemVerilog compiler
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SpinalhdlScala based HDL
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fpga-dockerTools for running FPGA vendor toolchains with Docker
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J1scA reimplementation of a tiny stack CPU
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EdalizeAn abstraction library for interfacing EDA tools
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VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
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SpinalDevDocker Development Environment for SpinalHDL
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FletcherFletcher: A framework to integrate FPGA accelerators with Apache Arrow
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kianRiscVKianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....
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