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→ Michaelvll
2 open source projects by Michaelvll
[ Open user page on Github ]
1.
Deepcca
An implementation of Deep Canonical Correlation Analysis (DCCA or Deep CCA) with pytorch.
✭ 125
python
2.
RISCV CPU
A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
✭ 48
c
Verilog
C++
assembly
Coq
SystemVerilog
verilog-hdl
risc-v
1-2
of
2
user projects
