Top 118 risc-v open source projects

Cycle-accurate pre-silicon simulator of RISC-V and MIPS CPUs

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

为推广RISC-V尽些薄力

Mirror; Work-in-progress software-rendering Vulkan implementation

Simple and lightweight source-based multi-platform Linux distribution with musl libc.

32-bit Superscalar RISC-V CPU

Where Lions Roam: RISC-V on the VELDT

A simple RISC-V processor for use in FPGA designs.

F# RISC-V Instruction Set formal specification

RISC-V CPU Core

🖥️ An xv6-like operating system on RISC-V with multi-core support. Documentation available online.

GD32V: development platform for PlatformIO

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

LicheeTang 蜂鸟E203 Core

C++17 RISC-V RV32GC / RV64GC userspace emulator library

All CPU and MCU documentation in one place

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

OpenEmbedded/Yocto layer for RISC-V Architecture

RISC-V instruction set simulator built for education

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

v3.5 https://rcore-os.github.io/rCore-Tutorial-Book-v3/

BL602 SDK. Any technical topic, please access the following link.

Compact FPGA game console

SweRV EL2 Core

RISC-V Instruction Set Simulator (Built for education).

FPGA-based RISC-V CPU+SoC.

TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

Kendryte K210: development platform for PlatformIO

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

MicroPython for K210 RISC-V, let's play with edge AI easier

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

Featherweight RISC-V implementation

Alphanumeric+1 shellcoding tools for RISC-V

Reko is a binary decompiler.

RT-Thread is an open source IoT operating system.

A graphical processor simulator and assembly editor for the RISC-V ISA

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

Renode - Antmicro's virtual development framework for complex embedded systems

The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

RISC-V Cores, SoC platforms and SoCs

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

RARS -- RISC-V Assembler and Runtime Simulator

SweRV EH1 core

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

The RISC-V software tools list, as seen on riscv.org

RISC-V Assembler and Runtime Simulator

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

A self-hosting and educational C compiler

OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

RISC-V CPU Core (RV32IM)

Maxine VM: A meta-circular research VM

A secure embedded operating system for microcontrollers

RISC-V processor emulator written in Rust+WASM

Nuclei Microcontroller Software Interface Standard Development Repo

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).