ECP5-PCIe / Ecp5 Pcie
Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
Stars: ✭ 49
Programming Languages
python
139335 projects - #7 most used programming language
Labels
Projects that are alternatives of or similar to Ecp5 Pcie
Iroha
Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
Stars: ✭ 30 (-38.78%)
Mutual labels: fpga
Audioxtreamer
ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.
Stars: ✭ 22 (-55.1%)
Mutual labels: fpga
Lxp32 Cpu
A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
Stars: ✭ 27 (-44.9%)
Mutual labels: fpga
Clash Compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
Stars: ✭ 958 (+1855.1%)
Mutual labels: fpga
Platformio Vscode Ide
PlatformIO IDE for VSCode: The next generation integrated development environment for IoT
Stars: ✭ 676 (+1279.59%)
Mutual labels: fpga
Fpga Fft
A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
Stars: ✭ 45 (-8.16%)
Mutual labels: fpga
Zbasic
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Stars: ✭ 27 (-44.9%)
Mutual labels: fpga
Tenyr
Simple, orthogonal 32-bit computer architecture and environment
Stars: ✭ 24 (-51.02%)
Mutual labels: fpga
Autooffload.jl
Automatic GPU, TPU, FPGA, Xeon Phi, Multithreaded, Distributed, etc. offloading for scientific machine learning (SciML) and differential equations
Stars: ✭ 21 (-57.14%)
Mutual labels: fpga
Image Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
Stars: ✭ 31 (-36.73%)
Mutual labels: fpga
Pipecnn
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
Stars: ✭ 775 (+1481.63%)
Mutual labels: fpga
Rsyocto
🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
Stars: ✭ 41 (-16.33%)
Mutual labels: fpga
Vexriscv
A FPGA friendly 32 bit RISC-V CPU implementation
Stars: ✭ 1,041 (+2024.49%)
Mutual labels: fpga
Higan Verilog
This is a higan/Verilator co-simulation example/framework
Stars: ✭ 35 (-28.57%)
Mutual labels: fpga
ECP5-PCIe
ECP5 to PCIe interface development
The goal of this project is to provide a PCIe interface in nMigen.
Previous work
There already exists a PCIe physical layer by whitequark called Yumewatari and a TLP and DMA layer by enjoy-digital called litepcie written in omigen.
TODO
- Read through Yumewatari and litepcie code
- Read more of the PCIe spec and summarize relevant parts
- Get an ECP5 device capable of PCIe
- Currently an adapter for the ECP5 EVN to PCIe is being built
INSTALL
Execute python setup.py develop in the Gateware folder
SETUP
https://github.com/ECP5-PCIe/ECP5-PCIe/wiki/Setup
If you have a Versa board, additionally run openocd -f ispCLOCK/ispCLOCK-200MHz.cfg to setup the ispCLOCK chip. For that you need to set J50 to connect pins 2-4 and 5-6. After you are done, set them back to 1-2 and 3-5.
RUN
- Enable PCIe on the connected device (for example on the ROCKPro64 execute
pci initin u-boot) - Execute
python test_pcie_phy.py runin the Tests folder to upload the gateware to the ECP5 - Execute
python test_pcie_phy.py grabto get DLLPs received in the L0 state (and the time since it has been in the L0 state). Sometimes the last few results are invalid and the program doesn't halt, end it by pressingCtrl + C. It should show something like this:
Data is composed of the first symbol received in one clock cycle, its representation in hexadecimal, the same for the second symbol. The time is in clock cycles since entering L0, which are 8 ns each.
Time since L0 | RX data | TX data | Temperature
Note that the project description data, including the texts, logos, images, and/or trademarks,
for each open source project belongs to its rightful owner.
If you wish to add or remove any projects, please contact us at [email protected].