fusesoc / Fusesoc Cores
FuseSoC standard core library
Stars: ✭ 41
Labels
Projects that are alternatives of or similar to Fusesoc Cores
Higan Verilog
This is a higan/Verilator co-simulation example/framework
Stars: ✭ 35 (-14.63%)
Mutual labels: verilog
Ethernet 10ge mac sv uvm tb
SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
Stars: ✭ 39 (-4.88%)
Mutual labels: verilog
Image Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
Stars: ✭ 31 (-24.39%)
Mutual labels: verilog
Riscv Megaproject
A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earlier ones
Stars: ✭ 29 (-29.27%)
Mutual labels: verilog
Alterade2labs verilog
My solutions to Alteras example labs
Stars: ✭ 40 (-2.44%)
Mutual labels: verilog
Ophidian
Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian
Stars: ✭ 32 (-21.95%)
Mutual labels: verilog
Verilog Utils
native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
Stars: ✭ 33 (-19.51%)
Mutual labels: verilog
Clash Compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
Stars: ✭ 958 (+2236.59%)
Mutual labels: verilog
Iroha
Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
Stars: ✭ 30 (-26.83%)
Mutual labels: verilog
Rsyocto
🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
Stars: ✭ 41 (+0%)
Mutual labels: verilog
Mojo Base Project
This is the base project for the Mojo. It should be used as the starting point for all projects.
Stars: ✭ 39 (-4.88%)
Mutual labels: verilog
FuseSoC standard core library
This is the standard core library to be used with FuseSoC
Installation
This library will be automatically cloned to ~/.local/share/fusesoc/fusesoc-cores
and added to fusesoc.conf when you run fusesoc init.
If you have a existing FuseSoC setup and the above does not work for you,
please consider this alternative installation method. Use git to clone
this repository and add it to your fusesoc.conf. For example in
~/.config/fusesoc/fusesoc.conf:
[main]
cores_root =
/home/joe/work/fusesoc-cores
cache_root = /home/joe/work/fuse-cache
build_root = /home/joe/work/fuse-builds
Contributing
Cores for FuseSoC should follow the following guidelines.
-
No Code Please do not store code in
fusesoc-cores. Please store your code in a separate repo or somewhere it can be fetched with theurlprovider. - If your core is really small please consider storing in the tiny-cores repo.
-
Stay Modern Use the modern sections in your core file like
filesetandparameter, please no obsoleteverilogsections. For details on migrating old cores to the current standard please refer to the FuseSoC migration guide. -
Versioning Each core should be versioned with either
- Versioned For cores where the upstream provider provides a release version, in git using tags is ideal, please use the corresponding release version.
-
Pseudo-versioned When an core's upstream provider is out of your
control and does not use versions please use version
0and point to a location which is unique for that revision (e.g. the sha for git repos or revision for svn repos instead of pointing to master, which might change over time). If you need to refer to a newer version of the upstream repo, still without a proper version, step the revision number (0-r1,0-r2..etc).
Note that the project description data, including the texts, logos, images, and/or trademarks,
for each open source project belongs to its rightful owner.
If you wish to add or remove any projects, please contact us at [email protected].