standardsemiconductor / Lion
Licence: bsd-3-clause
Where Lions Roam: RISC-V on the VELDT
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Programming Languages
haskell
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Where Lions Roam: RISC-V on the VELDT
Lion is a formally verified, 5-stage pipeline RISC-V core. Lion targets the VELDT FPGA development board and is written in Haskell using Clash.
This repository contains four parts:
- The Lion library: a pipelined RISC-V core.
- lion-formal: formally verify the core using riscv-formal.
- lion-soc: a System-on-Chip demonstrating usage of the Lion core on the VELDT.
- lion-metric: Observe Yosys synthesis metrics on the Lion Core.
Lion library
Usage:
- Add
lion
to build depends section of Cabal file - import module in source files
import Lion.Core
When connecting the core
to memory and peripherals, ensure single cycle latency.
Clone the repository
git clone https://github.com/standardsemiconductor/lion.git
cd lion
git submodule update --init
Features
Current Support
- Architecture: RV32I (no FENCE, ECALL, EBREAK)
- Configurable ALU adder and subtractor: use a generic (+) and (-) or SB_MAC16 hard IP
Future Support
All features will be added in a configurable manner extending the base RV32I configuration noted above
- Zicsr, Control and Status Register (CSR) Instructions
- CSR registers
- RV32IM
Check out the Lion Development project to see which features are in progress.
Note that the project description data, including the texts, logos, images, and/or trademarks,
for each open source project belongs to its rightful owner.
If you wish to add or remove any projects, please contact us at [email protected].