117 Open source projects that are alternatives of or similar to Lion

RARS -- RISC-V Assembler and Runtime Simulator

RISC-V CPU Core (RV32IM)

Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog

RISC-V Cores, SoC platforms and SoCs

A RISC-V 32bit single-cycle CPU written in Logisim

RISC-V Instruction Set Simulator (Built for education).

RISC-V Assembler and Runtime Simulator

OpenEmbedded/Yocto layer for RISC-V Architecture

Nuclei Microcontroller Software Interface Standard Development Repo

Featherweight RISC-V implementation

Renode - Antmicro's virtual development framework for complex embedded systems

The RISC-V software tools list, as seen on riscv.org

Compact FPGA game console

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

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SCR1 is a high-quality open-source RISC-V MCU core in Verilog

TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems

A self-hosting and educational C compiler

GD32V: development platform for PlatformIO

A secure embedded operating system for microcontrollers

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

A 32-bit RISC-V emulator in a shader (and C)

Reko is a binary decompiler.

PlatformIO is a professional collaborative platform for embedded development 👽 A place where Developers and Teams have true Freedom! No more vendor lock-in!

List of ideas for getting started with TimVideos projects

BL602 SDK. Any technical topic, please access the following link.

The Eclipse Embedded CDT plug-ins for Arm & RISC-V C/C++ developers (formerly known as the GNU MCU Eclipse plug-ins). Includes the archive of previous plug-ins versions, as Releases.

C++17 RISC-V RV32GC / RV64GC userspace emulator library

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SweRV EL2 Core

FireSim: Easy-to-use, Scalable, FPGA-accelerated Cycle-accurate Hardware Simulation in the Cloud

🖥️ An xv6-like operating system on RISC-V with multi-core support. Documentation available online.

SweRV EH1 core

FPGA-based RISC-V CPU+SoC.

The RISC-V software tools list, as seen on riscv.org

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Kendryte K210: development platform for PlatformIO

OS kernel labs based on Rust/C Lang & RISC-V 64/X86-32

F# RISC-V Instruction Set formal specification

Maxine VM: A meta-circular research VM

MicroPython for K210 RISC-V, let's play with edge AI easier

RISC-V processor emulator written in Rust+WASM

RISC-V instruction set simulator built for education

Port fpga-zynq (rocket-chip) to Xilinx ZYNQ Ultrascale+ board (ZCU102)

Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator used in FireSim.

A simple three-stage RISC-V CPU

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

Homebrew game for homebrew FPGA game console

Alphanumeric+1 shellcoding tools for RISC-V

⛔ DEPRECATED ⛔ HERO Software Development Kit

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

RT-Thread is an open source IoT operating system.

A simple RISC-V processor for use in FPGA designs.

RISC-V CPU Core

LicheeTang 蜂鸟E203 Core

v3.5 https://rcore-os.github.io/rCore-Tutorial-Book-v3/

A graphical processor simulator and assembly editor for the RISC-V ISA