Acorn BBC Micro on an Altera DE1 FPGA board

Example code for the Numato Opsis board, the first HDMI2USB production board.

SPI master and slave for FPGA written in VHDL

Haskell to VHDL/Verilog/SystemVerilog compiler

Digital FM Radio Receiver for FPGA

Donjon hardware tool for circuits security evaluation

VHDL Package for Sublime Text

A completely open source implementation of a Bitcoin Miner for Altera and Xilinx FPGAs. This project hopes to promote the free and open development of FPGA based mining solutions and secure the future of the Bitcoin project as a whole. A binary release is currently available for the Terasic DE2-115 Development Board, and there are compile-able projects for numerous boards.

A FPGA friendly 32 bit RISC-V CPU implementation

Image Processing Toolbox in Verilog using Basys3 FPGA

Ophidian's Mirror Repository on github. https://gitlab.com/eclufsc/eda/ophidian

A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm

A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set

Official repository of the AWS EC2 FPGA Hardware and Software Development Kit

VHDL-Mips-Pipeline-Microprocessor

VHDL Samples

27-Queens Puzzle: Massively Parellel Enumeration and Solution Counting

Caffe to VHDL

ReonV is a modified version of the Leon3, a synthesisable VHDL model of a 32-bit processor originally compliant with the SPARC V8 architecture, now changed to RISC-V ISA.