platform-shaktiShakti: development platform for PlatformIO
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RarsRARS -- RISC-V Assembler and Runtime Simulator
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Cores SwervSweRV EH1 core
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Ustc RvsocFPGA-based RISC-V CPU+SoC.
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LbforthSelf-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
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JupiterRISC-V Assembler and Runtime Simulator
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Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
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NMSISNuclei Microcontroller Software Interface Standard Development Repo
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Neorv32A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
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Meta RiscvOpenEmbedded/Yocto layer for RISC-V Architecture
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DiosixA lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V
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SheccA self-hosting and educational C compiler
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Maxine VmMaxine VM: A meta-circular research VM
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Scr1SCR1 is a high-quality open-source RISC-V MCU core in Verilog
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Riscv RustRISC-V processor emulator written in Rust+WASM
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ChipyardAn Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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hero-sdk⛔ DEPRECATED ⛔ HERO Software Development Kit
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bx-dockerTutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).
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Cores Swerv El2SweRV EL2 Core
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Riscv FsF# RISC-V Instruction Set formal specification
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