Riscv MiniSimple RISC-V 3-stage Pipeline in Chisel
Ckb VmCKB's vm, based on open source RISC-V ISA
PpciA compiler for ARM, X86, MSP430, xtensa and more implemented in pure Python
Riscv FsF# RISC-V Instruction Set formal specification
DanaDynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Riscv CardAn unofficial reference sheet for RISC-V.
Rvemu For BookReference implementation for the book "Writing a RISC-V Emulator in Rust".
RustsbiRISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem
RcoreRust version of THU uCore OS. Linux compatible.
DiosixA lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V
Meta RiscvOpenEmbedded/Yocto layer for RISC-V Architecture
Neorv32A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
Cva6The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
RiscyRiscy Processors - Open-Sourced RISC-V Processors
Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
VexriscvA FPGA friendly 32 bit RISC-V CPU implementation
K210 HalRust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!
Riscv BoomSonicBOOM: The Berkeley Out-of-Order Machine
CapstoneCapstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.
Rv8RISC-V simulator for x86-64
Cv32e40pCV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Probe RsA debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
ChipyardAn Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
RarsRARS -- RISC-V Assembler and Runtime Simulator
Scr1SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Pulp DronetA deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP
Riscv vhdlPortable RISC-V System-on-Chip implementation: RTL, debugger and simulators
F32cA 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
JupiterRISC-V Assembler and Runtime Simulator
LbforthSelf-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.
RvemuRISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).
SheccA self-hosting and educational C compiler
Maxine VmMaxine VM: A meta-circular research VM
Riscv RustRISC-V processor emulator written in Rust+WASM
TengineTengine is a lite, high performance, modular inference engine for embedded device
Ncnnncnn is a high-performance neural network inference framework optimized for the mobile platform
UnicornUnicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)
NMSISNuclei Microcontroller Software Interface Standard Development Repo
octoxxv6-riscv like OS written in Rust
QuasarQuasar 2.0: Chisel equivalent of SweRV-EL2
rustsbiRISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem
bx-dockerTutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).
rocc-softwareC/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)
interpInterpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining
hero-sdk⛔ DEPRECATED ⛔ HERO Software Development Kit
novuskA kernel written in Rust
araThe PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
cheribsdFreeBSD adapted for CHERI-RISC-V and Arm Morello.