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All Projects → Arlet → Verilog 6502

Arlet / Verilog 6502

A Verilog HDL model of the MOS 6502 CPU

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verilog

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A Verilog HDL version of the old MOS 6502 CPU.

Note: the 6502 core assumes a synchronous memory. This means that valid data (DI) is expected on the cycle after valid address. This allows direct connection to (Xilinx) block RAMs. When using asynchronous memory, I suggest registering the address/control lines for glitchless output signals.

Also check out my new 65C02 project

Have fun.

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