342 Open source projects that are alternatives of or similar to Verilog 6502

FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.

SoC design for Milkymist One - LM32, DDR SDRAM, 2D TMU, PFPU

Hardware implementation of the SHA-256 cryptographic hash function

open-source IEEE 802.11 WiFi baseband FPGA (chip) design

Connectal is a framework for software-driven hardware development.

MetroBoy - A playable, circuit-level simulation of an entire Game Boy

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

一步一步写MIPS CPU

NES in Verilog

SystemVerilog to Verilog conversion

Chisel 3: A Modern Hardware Design Language

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

Verilog SDRAM memory controller

All open source file and project for OpenFPGAduino project

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

LicheeTang 蜂鸟E203 Core

Recipe for FPGA cooking

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

BaseJump STL: A Standard Template Library for SystemVerilog

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Open source software for chip reverse engineering.

SystemVerilog language server

The Kestrel is a family of home-made computers, built as much as possible on open-source technology, and supporting as much as possible the open-source philosophy.

i8080 precise replica in Verilog, based on reverse engineering of real die

CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.

Various iCE40 cores / projects to play around with (mostly targeted at the icebreaker)

Test suite designed to check compliance with the SystemVerilog standard.

SystemVerilog parser library fully complient with IEEE 1800-2017

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

The USRP™ Hardware Driver FPGA Repository

iCESugar FPGA Board (base on iCE40UP5k)

CHIP-8 console on FPGA

This repository hosts the project for open-source hummingbird E203 RISC processor Core.

Verilog Generator of Neural Net Digit Detector for FPGA

Sythesizable, modular Verilog implementation of 802.11 OFDM decoder.

FPGA,Verilog,Python

A simple, basic, formally verified UART controller

Verilog UART

🌱 ❄️ Collection of open-source peripherals in Verilog

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

All code found on nandland is here. underconstruction.gif

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

PicoRV32 - A Size-Optimized RISC-V CPU

PDP-1 FPGA implementation in Verilog, with CRT, Teletype and Console.

A Verilog implementation of DisplayPort protocol for FPGAs

Open source design files for the TinyFPGA B-Series boards.

Verilog HDL/SystemVerilog/Bluespec SystemVerilog support for VS Code

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API.

FPGA/hardware design of openwifi

Verilog version of Z-scale (deprecated)

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:[email protected]

Core description files for FuseSoC

Verilog I2C interface for FPGA implementation

Repository for the SCALE-MAMBA MPC system

FPGA-based Nintendo Entertainment System Emulator

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Bus bridges and other odds and ends

A Compiler for the Popr Language

SystemVerilog compiler and language services