All Projects → lastweek → Fpga_readings

lastweek / Fpga_readings

Licence: apache-2.0
Recipe for FPGA cooking

Projects that are alternatives of or similar to Fpga readings

hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Stars: ✭ 145 (-11.59%)
Mutual labels:  fpga, hls, rtl, verilog
FPGA-USB-Device
FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
Stars: ✭ 29 (-82.32%)
Mutual labels:  fpga, rtl, verilog
Hard-JPEG-LS
FPGA-based JPEG-LS image compressor.
Stars: ✭ 52 (-68.29%)
Mutual labels:  fpga, rtl, verilog
Cores
Various HDL (Verilog) IP Cores
Stars: ✭ 271 (+65.24%)
Mutual labels:  verilog, fpga, rtl
sphinxcontrib-hdl-diagrams
Sphinx Extension which generates various types of diagrams from Verilog code.
Stars: ✭ 37 (-77.44%)
Mutual labels:  fpga, rtl, verilog
SpinalCrypto
SpinalHDL - Cryptography libraries
Stars: ✭ 36 (-78.05%)
Mutual labels:  fpga, rtl, verilog
Fake-SDcard
Imitate SDcard using FPGAs.
Stars: ✭ 26 (-84.15%)
Mutual labels:  fpga, rtl, verilog
SpinalDev
Docker Development Environment for SpinalHDL
Stars: ✭ 17 (-89.63%)
Mutual labels:  fpga, rtl, verilog
Spinalhdl
Scala based HDL
Stars: ✭ 696 (+324.39%)
Mutual labels:  verilog, fpga, rtl
Darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Stars: ✭ 1,062 (+547.56%)
Mutual labels:  verilog, fpga, rtl
Openwifi
open-source IEEE 802.11 WiFi baseband FPGA (chip) design
Stars: ✭ 2,257 (+1276.22%)
Mutual labels:  verilog, fpga, hls
virtio
Virtio implementation in SystemVerilog
Stars: ✭ 38 (-76.83%)
Mutual labels:  fpga, rtl, verilog
cnn open
A hardware implementation of CNN, written by Verilog and synthesized on FPGA
Stars: ✭ 157 (-4.27%)
Mutual labels:  fpga, rtl, verilog
vga-clock
Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.
Stars: ✭ 48 (-70.73%)
Mutual labels:  fpga, rtl, verilog
Logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Stars: ✭ 149 (-9.15%)
Mutual labels:  verilog, fpga, rtl
blarney
Haskell library for hardware description
Stars: ✭ 81 (-50.61%)
Mutual labels:  fpga, rtl, verilog
Openwifi Hw
FPGA/hardware design of openwifi
Stars: ✭ 181 (+10.37%)
Mutual labels:  verilog, fpga, hls
Verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
Stars: ✭ 296 (+80.49%)
Mutual labels:  verilog, fpga, rtl
Rggen
Code generation tool for configuration and status registers
Stars: ✭ 54 (-67.07%)
Mutual labels:  verilog, fpga, rtl
Ustc Rvsoc
FPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (-53.05%)
Mutual labels:  verilog, fpga, rtl
 _____ ____   ____    _    
|  ___|  _ \ / ___|  / \   
| |_  | |_) | |  _  / _ \  
|  _| |  __/| |_| |/ ___ \ 
|_|   |_|    \____/_/   \_\

Cook FPGA

This repository is intended for folks who are new and want to learn something about FPGA. This repository is a collection of useful resources and links rather than a thorough FPGA tutorial. Traditional HDL (Hard and Difficult Language) is not the main focus, instead, we focus on using high-level languages (e.g., C++) to cook FPGA.

Originally, this repository was started by a newbie to record his learning of FPGA, and late made public in the hope that it could help researchers to start their journey along with FPGA, with less pain and whiskey.

Resources collected here, or the way contents are organized, are not in their perfect shape. This repository is still raw and need major improvements. Any form of contribution is welcomed and appreciated.

Main contents:

  • README.md
    • Basics about Digital Design
    • Basics about FPGA
    • Relevant Courses and Books
    • Papers about FPGA internal
  • Xilinx
    • xilinx.md
    • xilinx_constraints.md
    • xilinx_cheatsheet.md
    • xilinx_lessons_vivado.md
    • xilinx_lessons_hls.md
  • submodules/: Github repositories about FPGA
  • hls/: Sample Xilinx HLS C++ code
    • AXI Stream
    • Network protocol processing
  • xilinx_arty_a7: Sample Xilinx projects for Arty A7 100 board
    • Tri-mode MAC reference design
    • Simple LED
    • Clocked LED
  • FAQ.md
    • Some implementation questions about FPGA

Resources

Papers

List of academic papers.

FPGA Intro

Digital Basics

Verilog

High-Level Synthesis (HLS)

Courses

Books

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].