All Projects → johan92 → verilog-coding-style

johan92 / verilog-coding-style

Licence: MIT license
Verilog (SystemVerilog) coding style

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verilog-coding-style

Это небольшой coding style, которым я руководствуюсь в FPGA проектах.

По факту, это набор правил, которые применялись при разработке в НТЦ Метротек.

см. сoding-style.md

Примеры расположены в директории examples.

При создании этого coding style принимали участие:

  • Иван Шевчук
  • Денис Габидуллин
  • Константин Добросолец
  • Алексей Литвинов
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