370 Open source projects that are alternatives of or similar to verilog-coding-style

A curated list of Coding Style Conventions and Standards.

Coding Guidelines for C#

XS-Labs Coding Style Guide for C, C++, Objective-C and x86 Assembly

OpenStaticAnalyzer is a source code analyzer tool, which can perform deep static analysis of the source code of complex systems.

MOXY eslint configuration to be used across several JavaScript projects

[READ-ONLY] PHP_CodeSniffer sniff that checks class name matches PSR-4 project structure.

Java coding style and template project used at Munich university of applied sciences

Write bulletproof JavaScript like a pro! 😎

Custom PHPCS sniffs to find Code Smells

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Yet Another RISC-V Implementation

FAST-9 Accelerator for Corner Detection

Generator of verilog description for FPGA MobileNet implementation

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

Simple 3-stage pipeline RISC-V processor

HDLBits website practices & solutions

Sphinx Extension which generates various types of diagrams from Verilog code.

Fork of OpenVeriFla - FPGA debugging logic analyzer to use with your designs - examples (so far) for ice40/IceStorm

🌊 Tide is a series of automated tests run against every WordPress.org theme and plugin

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.

FPGA Verilog implementation of 1949 EDSAC Computer with animated tape reader, panel, teleprinter and CRT scope

A formally verified high-level synthesis tool based on CompCert and written in Coq.

Facilitates building open source tools for working with hardware description languages (HDLs)

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Consistence - Coding Standard - PHP Code Sniffer rules

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

SpinalHDL - Cryptography libraries

Stylelint adapter for the Grunt task runner.

Coding-style checker for Epitech students. This program analyzes your C source files for Epitech coding-style violations.

INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

Vim plugin to aid VHDL development (for LSP, see https://github.com/suoto/hdl_checker)

MOS6581 SID chip emulator in SystemVerilog

Bazel build rules for Verilator

Naver JavaScript Coding Conventions rules for eslint

Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

Custom sniffs for PHP_CodeSniffer

NN on FPGA

Virtio implementation in SystemVerilog

Java coding specification (daily coding summary, standardizing project team members have a unified specification, convenient cooperation, error checking, refactoring, etc.) When you abandon the specification to write code as you like when you come back to read it, Remove all the impulses of rewriting.

A Hardware Construct Language

Simpler PHP code sniffer built on top of PHP-CS-Fixer.

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Reads a state transition system and performs property checking

Lattice iCE40: development platform for PlatformIO

🔧 Verilog plugin for Sublime Text 2/3. It helps to generate a simple testbench, instantiate a module, insert a user-header, repeat codes with formatted incremental/decremental numbers, etc.

Format style sheets according to the WordPress CSS coding standards.

Revengineered ancient PDP-11 CPUs, originals and clones

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

A parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.

PDP-6 Emulator

Programmable multichannel ADPCM decoder for FPGA

Standard Cell Library based Memory Compiler using FF/Latch cells

FPGA-based JPEG-LS image compressor.

A programming language for FPGAs.