327 Open source projects that are alternatives of or similar to fasm

SystemOT, yet another home brew cpu.

Generator of verilog description for FPGA MobileNet implementation

Dockerfile with Vivado for CI

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

Schematic symbol libraries for FPGAs & microcontrollers.

An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.

MOS6581 SID chip emulator in SystemVerilog

Unofficial Yosys WebAssembly packages

HDMI Out VHDL code for 7-series Xilinx FPGAs

High-speed LaserDisc RF sampler

This repository contains iCEBreaker examples for Amaranth HDL.

VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)

A Vivado HLS Command Line Helper Tool

SneakySnake🐍 is the first and the only pre-alignment filtering algorithm that works efficiently and fast on modern CPU, FPGA, and GPU architectures. It greatly (by more than two orders of magnitude) expedites sequence alignment calculation for both short and long reads. Described in the Bioinformatics (2020) by Alser et al. https://arxiv.org/abs…

Small Processing Unit 32: A compact RV32I CPU written in Verilog

Virtio implementation in SystemVerilog

RISC-V Cores, SoC platforms and SoCs

No-MMU Linux capable RISC-V SoC designed to be useful.

SASM - simple crossplatform IDE for NASM, MASM, GAS and FASM assembly languages

flat assembler 1 - reconstructed source history

Minimal .NET wrapper around the simple, easy to use Flat Assembler written by Tomasz Grysztar. Supports both x64 and x86 development.

Unofficial git history of flat assembler

User-mode Windows DLL injector written in Assembly language (FASM syntax) with WinAPI.

A hands-on introduction to video technology: image, video, codec (av1, vp9, h265) and more (ffmpeg encoding).

Test suite designed to check compliance with the SystemVerilog standard.

FOSS Flow For FPGA

Python interface to FPGA interchange format