327 Open source projects that are alternatives of or similar to fasm

Sphinx Extension which generates various types of diagrams from Verilog code.

Upduino v2 with the ice40 up5k FPGA demos

Project X-Ray Database: XC7 Series

Reference design for Lattice ECP5 FPGA. Featuring Raspberry Pi interface and 6 PMODs

Managed Machine Learning Systems and Internet of Things Live Lesson

Framework providing operating system abstractions and a range of shared networking (RDMA, TCP/IP) and memory services to common modern heterogeneous platforms.

shdl6800: A 6800 processor written in SpinalHDL

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

【原创，已被编入官方教材】Three-level storage subsystem(SD+DDR2 SDRAM+Cache), based on Nexys4 FPGA board. 同济大学计算机系统结构课程设计，FPGA三级存储子系统。

Xilinx Run Time for FPGA

Turning .NET assemblies into FPGA hardware for faster execution and lower power usage. See the Readme and https://hastlayer.com.

A re-creation of a Cosmac ELF computer, Coded in SpinalHDL

Cross EDA Abstraction and Automation

Fixed point package for Python.

The Task Parallel System Composer (TaPaSCo)

Docker Development Environment for SpinalHDL

Kansas Lava implementation of MOS 6502 microprocessor

A Forth CPU and System on a Chip, based on the J1, written in VHDL

iCE40 floorplan viewer

32-bit RISC-V system on chip for iCE40 and ECP5 FPGAs

SHA-256 IP core for ZedBoard (Zynq SoC)

P4-14/16 Bluespec Compiler

32-bit Superscalar RISC-V CPU

Polyphony is Python based High-Level Synthesis compiler.

Open source ultrasound processing modules and building blocks

An Open-source FPGA IP Generator

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

A programming language for FPGAs.

Show the time on a VGA monitor. Submitted for the Google MPW1 ASIC shuttle.

This project demonstrates DSP capabilities of Terasic DE2-115

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

👇 Add capacitive touch buttons to any FPGA!

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Verilog FPGA Parts Library. Old Octavo soft-CPU project.

A curated list of awesome open source hardware design tools

DMA attacks over PCI Express based on Xilinx Zynq-7000 series SoC

Tools for running FPGA vendor toolchains with Docker

Binary Neural Network on IceStick FPGA.

Must-have verilog systemverilog modules

Yet Another Tetris on FPGA Implementation

Bring Deep Learning to small devices

A hardware implementation of CNN, written by Verilog and synthesized on FPGA

CNN acceleration on virtex-7 FPGA with verilog HDL

Hands-on experience using the Vitis unified software platform with Xilinx FPGA hardware

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Random ideas and interesting ideas for things we hope to eventually do.

80186 compatible SystemVerilog CPU core and FPGA reference design

🔥 Technology-agnostic FPGA stress-test: maximum logic utilization and high dynamic power consumption.

Notes on the Red Pitaya Open Source Instrument

Materials for "Introduction to FPGA and Verilog" at MIPT DREC

Verilog Generator of Neural Net Digit Detector for FPGA

Small-scale Tensor Processing Unit built on an FPGA

Programmable multichannel ADPCM decoder for FPGA

FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)

Hex editor for bit-level occultism

FPGA/hardware design of openwifi

Bus bridges and other odds and ends

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Hardware definition library and environment for designing and building digital hardware for FPGAs, using only open source tools

Lattice iCE40: development platform for PlatformIO