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Top 2 pipelined open source projects

FPGA RealTime and Static Sobel Edge Detection

Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images

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Verilog real-time fpga static verilog ov7670 pipelined sobel-edge-detector

KianRISC-V! No RISC-V, no fun! RISC-V CPU with strong design rules and unittested! CPU you can trust! kianv rv32im risc-v a hdmi soc with harris computer architecture in verilog: multicycle, singlecycle and 5-stage pipelining Processor. Multicycle Soc with firmware that runs raytracer, mandelbrot, 3d hdmi gfx, dma controller, etc.....

✭ 167

AGS Script assembly c Verilog tcl SystemVerilog cpu fpga riscv verilog breakout divider ice40 ds3231 multiplier icoboard icebreaker pipelined ecp5 rv32im ice40hx1k ulx3s icefun softcpu sd1306 sd1331

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