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Top 2 timing-analysis open source projects

This is a tutorial on standard digital design flow

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tcl Makefile Verilog synthesis synopsys logic-synthesis verilog-hdl timing-analysis

OpenROAD-flow-scripts

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

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Verilog SourcePawn tcl python Makefile shell eda rtl verilog def gdsii timing-analysis openroad lef opendb-database

1-2 of 2 timing-analysis projects