Top 100 rtl open source projects

React Datepicker
An easily internationalizable, accessible, mobile-friendly datepicker library for the web, build with styled-components.
Framevuerk
Fast, Responsive, Multi Language, Both Direction Support and Configurable UI Framework based on Vue.js.
Axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Riscv Mini
Simple RISC-V 3-stage Pipeline in Chisel
Awesome Learning
Awesome Learning - Learn JavaScript and Front-End Fundamentals at your own pace
Hugo Theme Bootstrap4 Blog
A blogging-centric Bootstrap v4 theme for the Hugo static site generator.
React With Direction
Components to provide and consume RTL or LTR direction in React
Fpga readings
Recipe for FPGA cooking
Dana
Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
Kastrifree
Free version of the Kastri library
Tailwindcss Dir
Adds direction (LTR, RTL) variants to your Tailwind project
Logic
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Postcss Rtl
PostCSS plugin for RTL-adaptivity
Chisel3
Chisel 3: A Modern Hardware Design Language
Pinlayout
Fast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]
Tailwindcss Rtl
Enabling bidirectional support on tailwindcss framework
Sv Tests
Test suite designed to check compliance with the SystemVerilog standard.
✭ 108
verilogrtl
Sb Admin2
this is an RTL Version of sb-admin2 Template, one of free template series in startbootstrap.com , (download remain file from startbootstrap.com)
✭ 107
htmlrtl
Bootstrap Rtl
Bootstrap RTL Standard 3 and 4
Rtlcss
Framework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)
Ustc Rvsoc
FPGA-based RISC-V CPU+SoC.
Actionbarrtlizer
Do you want RTL ActionBar? So you've found a library that can RTLize android's "ActionBar"!
Rggen
Code generation tool for configuration and status registers
Darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Bootstrap Star Rating
A simple yet powerful JQuery star rating plugin with fractional rating support.
Perfect Chisel
Chisel artifacts developed under IBM's involvement with the DARPA PERFECT program
✭ 20
scalartl
Riscv Boom
SonicBOOM: The Berkeley Out-of-Order Machine
Postcss Start To End
PostCSS plugin that lets you control your layout (LTR or RTL) through logical rather than physical rules
Spinalhdl
Scala based HDL
Salamandra
Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.
Leku
🌍 Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.
Chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Bootstrap V4 Rtl
RTL edition of bootstrap v4 for rtl languages like Farsi and Arabic
Mylinearlayout
MyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITab…
Scr1
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Recycler View Divider
A library which configures a divider for a RecyclerView.
Rtl Viewpager
ViewPager with RTL support 🔄
Awesome Arabic
A curated list of awesome projects and dev/design resources for supporting Arabic computational needs.
Verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
Openlane
OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
Openroad
OpenROAD's unified application implementing an RTL-to-GDS Flow
Cores
Various HDL (Verilog) IP Cores
sv-tests
Test suite designed to check compliance with the SystemVerilog standard.
blarney
Haskell library for hardware description
odoo-rtl
Odoo (OpenERP) Right to left support for User Interface, report and frontend
web-starter-kit
An opinionated starter kit with styled-system, graphql-hooks, mobx and nextjs (PWA)
honeywell-wireless-doorbell
Understanding the RF signal used in the Honeywell RCWL300A, RCWL330A, Series 3, 5, 9 and Decor Series Wireless Chimes
hwt
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
1-60 of 100 rtl projects