React DatepickerAn easily internationalizable, accessible, mobile-friendly datepicker library for the web, build with styled-components.
FramevuerkFast, Responsive, Multi Language, Both Direction Support and Configurable UI Framework based on Vue.js.
AxiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Riscv MiniSimple RISC-V 3-stage Pipeline in Chisel
Awesome LearningAwesome Learning - Learn JavaScript and Front-End Fundamentals at your own pace
DanaDynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
LogicCMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
Chisel3Chisel 3: A Modern Hardware Design Language
PinlayoutFast Swift Views layouting without auto layout. No magic, pure code, full control and blazing fast. Concise syntax, intuitive, readable & chainable. [iOS/macOS/tvOS/CALayer]
Sv TestsTest suite designed to check compliance with the SystemVerilog standard.
Sb Admin2this is an RTL Version of sb-admin2 Template, one of free template series in startbootstrap.com , (download remain file from startbootstrap.com)
RtlcssFramework for transforming Cascading Style Sheets (CSS) from Left-To-Right (LTR) to Right-To-Left (RTL)
ActionbarrtlizerDo you want RTL ActionBar? So you've found a library that can RTLize android's "ActionBar"!
RggenCode generation tool for configuration and status registers
Darkriscvopensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Perfect ChiselChisel artifacts developed under IBM's involvement with the DARPA PERFECT program
Riscv BoomSonicBOOM: The Berkeley Out-of-Order Machine
Postcss Start To EndPostCSS plugin that lets you control your layout (LTR or RTL) through logical rather than physical rules
SalamandraSalamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.
Leku🌍 Map location picker component for Android. Based on Google Maps. An alternative to Google Place Picker.
ChipyardAn Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Bootstrap V4 RtlRTL edition of bootstrap v4 for rtl languages like Farsi and Arabic
MylinearlayoutMyLayout is a powerful iOS UI framework implemented by Objective-C. It integrates the functions with Android Layout,iOS AutoLayout,SizeClass, HTML CSS float and flexbox and bootstrap. So you can use LinearLayout,RelativeLayout,FrameLayout,TableLayout,FlowLayout,FloatLayout,PathLayout,GridLayout,LayoutSizeClass to build your App 自动布局 UIView UITab…
Scr1SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Awesome ArabicA curated list of awesome projects and dev/design resources for supporting Arabic computational needs.
VerilogRepository for basic (and not so basic) Verilog blocks with high re-use potential
OpenlaneOpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.
OpenroadOpenROAD's unified application implementing an RTL-to-GDS Flow
CoresVarious HDL (Verilog) IP Cores
sv-testsTest suite designed to check compliance with the SystemVerilog standard.
blarneyHaskell library for hardware description
odoo-rtlOdoo (OpenERP) Right to left support for User Interface, report and frontend
QuasarQuasar 2.0: Chisel equivalent of SweRV-EL2
ofdmChisel Things for OFDM
web-starter-kitAn opinionated starter kit with styled-system, graphql-hooks, mobx and nextjs (PWA)
FPGA-USB-DeviceFPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.
honeywell-wireless-doorbellUnderstanding the RF signal used in the Honeywell RCWL300A, RCWL330A, Series 3, 5, 9 and Decor Series Wireless Chimes
hwtVHDL/Verilog/SystemC code generator, simulator API written in python/c++