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All Projects → lisper → Cpus Caddr

lisper / Cpus Caddr

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

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verilog

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cpus-caddr

Verilog FPGA re-implementation of MIT CADR lisp machine

This is a re-write of the MIT CADR verilog, with more rational clocking and synchronous rams.

It includes a little nios cpu which was used to debug the dram and mmc code.

It boots a load band and runs as a lisp machine.

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