Reiuiji / Ece368 Lab
Licence: mit
ECE368 | Lab
Projects that are alternatives of or similar to Ece368 Lab
EdalizeAn abstraction library for interfacing EDA tools
Stars: ✭ 270 (+4400%)
Mutual labels: vhdl
Parallella ExamplesCommunity created parallella projects
Stars: ✭ 384 (+6300%)
Mutual labels: vhdl
SpinalhdlScala based HDL
Stars: ✭ 696 (+11500%)
Mutual labels: vhdl
Dsi ShieldArduino MIPI DSI Shield
Stars: ✭ 330 (+5400%)
Mutual labels: vhdl
Riscv vhdlPortable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Stars: ✭ 356 (+5833.33%)
Mutual labels: vhdl
GcvideoGameCube Digital AV converter
Stars: ✭ 385 (+6316.67%)
Mutual labels: vhdl
Opl3 fpgaReverse engineered SystemVerilog RTL version of the Yamaha OPL3 (YMF262) FM Synthesizer
Stars: ✭ 255 (+4150%)
Mutual labels: vhdl
MicrowattA tiny Open POWER ISA softcore written in VHDL 2008
Stars: ✭ 383 (+6283.33%)
Mutual labels: vhdl
GplgpuGPL v3 2D/3D graphics engine in verilog
Stars: ✭ 515 (+8483.33%)
Mutual labels: vhdl
F32cA 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz
Stars: ✭ 338 (+5533.33%)
Mutual labels: vhdl
Mist BoardCore sources and tools for the MIST board
Stars: ✭ 350 (+5733.33%)
Mutual labels: vhdl
Parallella HwParallella board design files
Stars: ✭ 389 (+6383.33%)
Mutual labels: vhdl
HalHAL – The Hardware Analyzer
Stars: ✭ 298 (+4866.67%)
Mutual labels: vhdl
Cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Stars: ✭ 740 (+12233.33%)
Mutual labels: vhdl
Csi2rxOpen Source 4k CSI-2 Rx core for Xilinx FPGAs
Stars: ✭ 266 (+4333.33%)
Mutual labels: vhdl
Awesome HdlHardware Description Languages
Stars: ✭ 385 (+6316.67%)
Mutual labels: vhdl
Sha 256 HdlAn implementation of original SHA-256 hash function in (RTL) VHDL
Stars: ✭ 6 (+0%)
Mutual labels: vhdl
Fpga webserverA work-in-progress for what is to be a software-free web server for static content.
Stars: ✭ 762 (+12600%)
Mutual labels: vhdl
VunitVUnit is a unit testing framework for VHDL/SystemVerilog
Stars: ✭ 438 (+7200%)
Mutual labels: vhdl
ECE368 Advanced Digital Design Lab
Welcome to the ECE368 Lab Repository.
This repository contains setup instructions, VHDL examples, Lab assignments and the Final Project for ECE368. ECE368 is an Advanced Digital Design Course focusing on VHDL with a FPGA.
Lab Requirements:
- Nexyx 2 Development Board
- ISE WebPack 14.7
- Group with a classmate(2-3 per group)
Lab Code
The lab code that was provided for each lab is designed as a learning mechanism. The code has issue's on purpose and its up to you to find the issues. Solution for the code for each lab will be handed out upon request after the completion of the lab assignment.
Hardware
The course will focus primary on Digilent's Nexys™2 Spartan-3E FPGA Board as a learning tool.
Software
The course will use Xilinx's 14.7 ISE WebPack Edition. The webpack edition is free to download and use. But first you have to register on their site to download it and obtain a webpack license.
Lab Schedule
| Lab# |
Topic |
Course Date |
Due Date |
| [1](Lab 1/Lab1.pdf) |
Intro |
2016-01-29 |
2016-02-12 |
| [2](Lab 2/Lab2.pdf) |
Input |
2016-02-12 |
2016-02-19 |
| [3](Lab 3/Lab3.pdf) |
Output |
2016-02-19 |
2016-02-26 |
| [4](Lab 4/Lab4.pdf) |
Debug |
2016-02-26, 2016-03-04 |
2016-03-11 |
Project Schedule
| Part# |
Topic |
Course Date |
Due Date |
| [1](Project Lab 1/ProjectLab1.pdf) |
Control Path, Data Path |
2016-03-11, 2016-03-25 |
2016-04-01 |
| [2](Project Lab 2/ProjectLab2.pdf) |
Branch, Jump Link, Return, Interrupt |
2016-04-01, 2016-04-08 |
2016-04-15 |
| [3](Project Lab 3/ProjectLab3.pdf) |
Finalization of RISC |
2016-04-15, 2016-04-22 |
2016-05-06 |
Download and use
This Git Repo uses git-lfs to maintain large binary files. To download the entire repo first install git-lfs and run git clone [repo]. It is recomend to run git lfs pull after you git clone to Fetch LFS changes in the repo and show the contents properly.
Contributors
Resources
license
The course material presented are available under the MIT License.
Note that the project description data, including the texts, logos, images, and/or trademarks,
for each open source project belongs to its rightful owner.
If you wish to add or remove any projects, please contact us at
[email protected].
