GitPlanet

Cheap and reliable Node.js hosting starts at $3/month, and $1/month static HTML hosting

Created with love in Canada, visit hostnodejs.com today

Feel like to post an Ad? Learn Details
All Projects → f32c → F32c

f32c / F32c

Licence: bsd-2-clause
A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

Labels

arduinofpgavhdlriscvmips

Projects that are alternatives of or similar to F32c

Neorv32
A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
Stars: ✭ 106 (-68.64%)
Mutual labels:  fpga, vhdl, riscv
Vexriscv
A FPGA friendly 32 bit RISC-V CPU implementation
Stars: ✭ 1,041 (+207.99%)
Mutual labels:  fpga, vhdl, riscv
PoC-Examples
This repository contains synthesizable examples which use the PoC-Library.
Stars: ✭ 27 (-92.01%)
Mutual labels:  fpga, vhdl
QNICE-FPGA
QNICE-FPGA is a 16-bit computer system for recreational programming built as a fully-fledged System-on-a-Chip in portable VHDL.
Stars: ✭ 51 (-84.91%)
Mutual labels:  fpga, vhdl
getting-started
List of ideas for getting started with TimVideos projects
Stars: ✭ 50 (-85.21%)
Mutual labels:  fpga, vhdl
noasic
An open-source VHDL library for FPGA design.
Stars: ✭ 27 (-92.01%)
Mutual labels:  fpga, vhdl
JSON-for-VHDL
A JSON library implemented in VHDL.
Stars: ✭ 56 (-83.43%)
Mutual labels:  fpga, vhdl
riscv-contest-2018
RISCV SoftCPU Contest 2018
Stars: ✭ 14 (-95.86%)
Mutual labels:  fpga, riscv
SpinalCrypto
SpinalHDL - Cryptography libraries
Stars: ✭ 36 (-89.35%)
Mutual labels:  fpga, vhdl
fpga puf
🔑 Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
Stars: ✭ 44 (-86.98%)
Mutual labels:  fpga, vhdl
interp
Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining
Stars: ✭ 32 (-90.53%)
Mutual labels:  mips, riscv
intfftk
Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.
Stars: ✭ 43 (-87.28%)
Mutual labels:  fpga, vhdl
KyogenRV
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Stars: ✭ 37 (-89.05%)
Mutual labels:  fpga, riscv
yarvi
Yet Another RISC-V Implementation
Stars: ✭ 59 (-82.54%)
Mutual labels:  fpga, riscv
Fuxi
Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
Stars: ✭ 68 (-79.88%)
Mutual labels:  fpga, riscv
TinyMIPS
The Project TinyMIPS is dedicated to enabling undergraduates to build a complete computer system from scratch.
Stars: ✭ 29 (-91.42%)
Mutual labels:  fpga, mips
math
Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)
Stars: ✭ 15 (-95.56%)
Mutual labels:  fpga, vhdl
Edalize
An abstraction library for interfacing EDA tools
Stars: ✭ 270 (-20.12%)
Mutual labels:  fpga, vhdl
BenEaterVHDL
VHDL project to run a simple 8-bit computer very similar to the one built by Ben Eater (see https://eater.net)
Stars: ✭ 30 (-91.12%)
Mutual labels:  fpga, vhdl
vhdl-hdmi-out
HDMI Out VHDL code for 7-series Xilinx FPGAs
Stars: ✭ 36 (-89.35%)
Mutual labels:  fpga, vhdl
View All Similar Projects ➔

f32c

f32c is a retargetable, scalar, pipelined, 32-bit processor core which can execute subsets of either RISC-V or MIPS instruction sets. It is implemented in parametrized VHDL which permits synthesis with different area / speed tradeoffs, and includes a branch predictor, exception handling control block, and optional direct-mapped caches. The RTL code also includes SoC modules such as a multi-port SDRAM and SRAM controllers, video framebuffers with composite (PAL), HDMI, DVI and VGA outputs with simple 2D acceleration for sprites and windows, floating point vector processor, SPI, UART, PCM audio, GPIO, PWM outputs and a timer, as well as glue logic tailored for numerous popular FPGA development boards from various manufacturers.

In synthetic integer benchmarks the core yields 3.06 CoreMark/MHz and 1.63 DMIPS/MHz (1.81 DMIPS/MHz with function inlining) with code and data stored in on-chip block RAMs. When configured with 16 KB of instruction and 4 KB of data cache, and with code and data stored in external SDRAM, the core yields 2.78 CoreMark/MHz and 1.31 DMIPS/MHz.

A performance-tuned f32c SoC which includes a timer and an UART occupies only 1048 6-input LUTs, while still being able to execute gcc-generated code when synthesized in the most compact configuration which consumes just 697 (649 logic plus 48 memory) LUTs.

Floating point vector processor can be optionally synthesized. Tested on Xilinx Spartan-6 (xc6slx25) and 7-series (xc7a35i, xc7a102t, xc7z010), Altera Cyclone-4 (EP4CE22) and MAX-10 (10M50DAF), Lattice ECP3 (LFE3-150EA) and ECP5 (LFE5UM-85F). On Artix-7 it uses 3148 LUTs, 64K BRAM, 38 DSP multipliers (36 for divider unit) and can provide up to 3 MFLOPs/MHz.

The Fmax depends on core configuration and FPGA silicon, and tops at around 115 MHz for 90 nm FPGAs (such as Xilinx S3E / S3A or Lattice XP2) up to 185 MHz for latest generations of 6-input LUT FPGAs such as Artix-7.

Configurable options include:

C_arch               RISC-V or MIPS ISA
C_big_endian         bus endianess
C_mult_enable        synthesize multipler unit
C_branch_likely      support branch delay slot annulling
C_sign_extend        support sign extension instructions
C_movn_movz          support conditional move instructions
C_ll_sc              support atomic read-modify-write constructs
C_branch_prediction  synthesize branch predictor
C_bp_global_depth    global branch history trace size
C_result_forwarding  synthesize result bypasses
C_load_aligner 	     synthesize load aligner
C_full_shifter 	     pipelined instead of iterative shifer
C_icache_size        instruction cache size (0 to 64 KB)
C_dcache_size        data cache size (0 to 64 KB)
C_debug              synthesize single-stepping debug module

Pre-compiled gcc-based toolchains for Windows, OS-X and Linux can be found at the FPGArduino page, together with pre-built demo bitstreams for various Xilinx, Altera and Lattice FPGAs, and with further instructions on how to compile RISC-V / MIPS executables using the Arduino IDE.

All VHDL modules are BSD licensed. The majority of software libraries are borrowed from FreeBSD, while some originate from other projects and may be subject to an MIT-style license.

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].