All Projects → MiSTer-devel → Genesis_mister

MiSTer-devel / Genesis_mister

Licence: gpl-3.0
Sega Genesis for MiSTer

Labels

Projects that are alternatives of or similar to Genesis mister

H265 Encoder Rtl
Stars: ✭ 48 (-36%)
Mutual labels:  verilog
Practical Uvm Step By Step
This is the main repository for all the examples for the book Practical UVM
Stars: ✭ 56 (-25.33%)
Mutual labels:  verilog
Jt gng
CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.
Stars: ✭ 65 (-13.33%)
Mutual labels:  verilog
Wbscope
A wishbone controlled scope for FPGA's
Stars: ✭ 50 (-33.33%)
Mutual labels:  verilog
Rggen
Code generation tool for configuration and status registers
Stars: ✭ 54 (-28%)
Mutual labels:  verilog
Cdbus ip
CDBUS Protocol and the IP Core for FPGA users
Stars: ✭ 60 (-20%)
Mutual labels:  verilog
Cnn hardware acclerator for fpga
This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs
Stars: ✭ 47 (-37.33%)
Mutual labels:  verilog
Vt52 Fpga
Stars: ✭ 75 (+0%)
Mutual labels:  verilog
Fpga101 Workshop
FPGA 101 - Workshop materials
Stars: ✭ 54 (-28%)
Mutual labels:  verilog
J1sc
A reimplementation of a tiny stack CPU
Stars: ✭ 64 (-14.67%)
Mutual labels:  verilog
Up5k basic
A small 6502 system with MS BASIC in ROM
Stars: ✭ 51 (-32%)
Mutual labels:  verilog
Electron
A mixed signal netlist language (pre-alpha)
Stars: ✭ 52 (-30.67%)
Mutual labels:  verilog
Ao68000
The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
Stars: ✭ 60 (-20%)
Mutual labels:  verilog
Vexriscv
A FPGA friendly 32 bit RISC-V CPU implementation
Stars: ✭ 1,041 (+1288%)
Mutual labels:  verilog
Symbiflow Examples
Example designs showing different ways to use SymbiFlow toolchains.
Stars: ✭ 71 (-5.33%)
Mutual labels:  verilog
Hw
RTL, Cmodel, and testbench for NVDLA
Stars: ✭ 1,041 (+1288%)
Mutual labels:  verilog
Riscy Soc
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
Stars: ✭ 59 (-21.33%)
Mutual labels:  verilog
Computerarchitecturelab
This repository is used to release the Labs of Computer Architecture Course from USTC
Stars: ✭ 75 (+0%)
Mutual labels:  verilog
Cpus Caddr
FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs
Stars: ✭ 72 (-4%)
Mutual labels:  verilog
Core jpeg
High throughput JPEG decoder in Verilog for FPGA
Stars: ✭ 64 (-14.67%)
Mutual labels:  verilog

SEGA Megadrive/Genesis for MiSTer Platform

This is the port of the fpgagen core.

fpgagen - a SEGA Megadrive/Genesis clone in a FPGA. Copyright (c) 2010-2013 Gregory Estrade ([email protected]) All rights reserved

Installing

copy .rbf to root of SD card. Put some ROMs (.BIN/.GEN/.MD) into Genesis folder

Hot Keys

  • F1 - reset to JP(NTSC) region
  • F2 - reset to US(NTSC) region
  • F3 - reset to EU(PAL) region

Auto Region option

There are 2 versions of region detection:

  1. File name extension:
  • BIN -> JP
  • GEN -> US
  • MD -> EU
  1. Header. It may not always work as not all ROMs follow the rule, especially in European region. The header may include several regions - the correct one will be selected depending on priority option.

Additional features

  • Multitaps: 4-way, Team player, J-Cart
  • SVP chip (Virtua Racing)
  • Audio Filters for Model 1, Model 2, Minimal, No Filter.
  • Option to choose between YM2612 and YM3438 (changes Ladder Effect behavior).
  • Composite Blending, smooth dithering patterns in games.
  • Sprite Limit, enables more sprites.
  • CPU Turbo, mitigates slowdowns.
Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].