Sega Genesis for MiSTer

A single-wire bi-directional chip-to-chip interface for FPGAs

Regression test suite for Icarus Verilog.

Homotopy theory in Coq.

Bitcoin miner for Xilinx FPGAs

FuseSoC-based SoC for SweRV EH1

A very primitive but hopefully self-educational CPU in Verilog

Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools

FPGA-based RISC-V CPU+SoC.

FPGA-based C64 Accelerator / C65 like computer

IC design and development should be faster，simpler and more reliable

The Antikernel operating system project

A low pin count sniffer for ICEStick - targeting TPM chips

This repository is used to release the Labs of Computer Architecture Course from USTC

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

Compact FPGA game console

FPGA implementation of Cellular Neural Network (CNN)

A nicer HDL.