All Projects → azonenberg → Antikernel

azonenberg / Antikernel

The Antikernel operating system project

Projects that are alternatives of or similar to Antikernel

Rsyocto
🤖 SoCFPGA: Open Source embedded Linux developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
Stars: ✭ 41 (-45.33%)
Mutual labels:  verilog, fpga
Wbscope
A wishbone controlled scope for FPGA's
Stars: ✭ 50 (-33.33%)
Mutual labels:  verilog, fpga
Hrm Cpu
Human Resource Machine - CPU Design #HRM
Stars: ✭ 43 (-42.67%)
Mutual labels:  verilog, fpga
Image Processing
Image Processing Toolbox in Verilog using Basys3 FPGA
Stars: ✭ 31 (-58.67%)
Mutual labels:  verilog, fpga
Fpga101 Workshop
FPGA 101 - Workshop materials
Stars: ✭ 54 (-28%)
Mutual labels:  verilog, fpga
Higan Verilog
This is a higan/Verilator co-simulation example/framework
Stars: ✭ 35 (-53.33%)
Mutual labels:  verilog, fpga
Symbiflow Examples
Example designs showing different ways to use SymbiFlow toolchains.
Stars: ✭ 71 (-5.33%)
Mutual labels:  verilog, fpga
Zbasic
A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
Stars: ✭ 27 (-64%)
Mutual labels:  verilog, fpga
Rggen
Code generation tool for configuration and status registers
Stars: ✭ 54 (-28%)
Mutual labels:  verilog, fpga
Electron
A mixed signal netlist language (pre-alpha)
Stars: ✭ 52 (-30.67%)
Mutual labels:  verilog, fpga
Clash Compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
Stars: ✭ 958 (+1177.33%)
Mutual labels:  verilog, fpga
J1sc
A reimplementation of a tiny stack CPU
Stars: ✭ 64 (-14.67%)
Mutual labels:  verilog, fpga
Icestudio
❄️ Visual editor for open FPGA boards
Stars: ✭ 958 (+1177.33%)
Mutual labels:  verilog, fpga
Mips Cpu
A MIPS CPU implemented in Verilog
Stars: ✭ 38 (-49.33%)
Mutual labels:  verilog, fpga
Iroha
Intermediate Representation Of Hardware Abstraction (LLVM-ish for HLS)
Stars: ✭ 30 (-60%)
Mutual labels:  verilog, fpga
Vexriscv
A FPGA friendly 32 bit RISC-V CPU implementation
Stars: ✭ 1,041 (+1288%)
Mutual labels:  verilog, fpga
Spinalhdl
Scala based HDL
Stars: ✭ 696 (+828%)
Mutual labels:  verilog, fpga
Hdl
HDL libraries and projects
Stars: ✭ 727 (+869.33%)
Mutual labels:  verilog, fpga
Darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Stars: ✭ 1,062 (+1316%)
Mutual labels:  verilog, fpga
Core jpeg
High throughput JPEG decoder in Verilog for FPGA
Stars: ✭ 64 (-14.67%)
Mutual labels:  verilog, fpga

Antikernel

This is the new development repository for the Antikernel OS.

Project Roadmap:

In no particular order...

Eventually some of these TODOs will be broken down into tickets on the issue tracker. Need to work out some finer details on design first.

  • The legacy Splash build system is being completely rewritten and replaced.
  • We'd love to write some developer documentation and formally specify the APIs for various existing components, as well as writing specifications for not-yet-implemented peripherals/drivers/services
  • Fix the SARATOGA L1 cache so the miss servicing latency isn't so bad.
  • Reduce hazards between SARATOGA execution units so we can dual-issue a higher fraction of instructions.
  • Experiment with porting Antikernel to a Xilinx Zynq SoC using both the Cortex-A9s and the FPGA.
  • We should probably have a filesystem at some point.

Stuff you might be interested in:

NOTES

The "legacy-*" directories contain a raw export of the old Subversion repository. This will all get moved elsewhere, possibly to separate repositories, during the upcoming restructuring.

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].