jamieiles / Oldland Cpu
Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools
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Oldland CPU
Oldland is a 32-bit RISC CPU targeted at FPGAs. The main features are:
- 5 stage load/store pipeline.
- 16 general purpose registers.
- N-way set-associative blocking instruction/data caches
- Software managed instruction/data TLBs with 4KB page size.
- JTAG debug controller for execution control and state modification/inspection.
- Exception table for interrupts, data/instruction aborts, illegal instruction and software interrupts along with separate ITLB/DTLB miss handlers.
- User and supervisor modes.
Keynsham is a SoC using Oldland as the core and has a number of peripherals:
- 32MB SDR SDRAM controller.
- SPI master with configurable number of chip selects.
- On-chip bootrom.
- On-chip memory.
- Programmable timers.
- Interrupt controller.
- UART.
- SPI master.
- GPIO.
There is a C model along with Icarus and Verilator RTL simulations. The Keynsham SoC can be synthesized to run on a Terasic DE0 Nano or DE0-CV. There are ports of binutils, gcc and u-boot available.
For documentation see the Oldland CPU site
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