GitPlanet

Cheap and reliable Node.js hosting starts at $3/month, and $1/month static HTML hosting

Created with love in Canada, visit hostnodejs.com today

Feel like to post an Ad? Learn Details
All Projects → kunalg123 → Vsdflow

kunalg123 / Vsdflow

Licence: apache-2.0
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.

Labels

verilog

Projects that are alternatives of or similar to Vsdflow

Riscy Soc
Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
Stars: ✭ 59 (-28.05%)
Mutual labels:  verilog
Vt52 Fpga
Stars: ✭ 75 (-8.54%)
Mutual labels:  verilog
Toooba
RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
Stars: ✭ 79 (-3.66%)
Mutual labels:  verilog
Ao68000
The OpenCores ao68000 IP Core is a Motorola MC68000 binary compatible processor.
Stars: ✭ 60 (-26.83%)
Mutual labels:  verilog
Symbiflow Examples
Example designs showing different ways to use SymbiFlow toolchains.
Stars: ✭ 71 (-13.41%)
Mutual labels:  verilog
Genesis mister
Sega Genesis for MiSTer
Stars: ✭ 75 (-8.54%)
Mutual labels:  verilog
Fpga101 Workshop
FPGA 101 - Workshop materials
Stars: ✭ 54 (-34.15%)
Mutual labels:  verilog
Cpu
A very primitive but hopefully self-educational CPU in Verilog
Stars: ✭ 80 (-2.44%)
Mutual labels:  verilog
Cpus Caddr
FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs
Stars: ✭ 72 (-12.2%)
Mutual labels:  verilog
Ustc Rvsoc
FPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (-6.1%)
Mutual labels:  verilog
Core jpeg
High throughput JPEG decoder in Verilog for FPGA
Stars: ✭ 64 (-21.95%)
Mutual labels:  verilog
Jt gng
CAPCOM arcade hardware accurately replicated on MiST and MiSTer FPGA platforms. It covers Ghosts'n Goblins, 1942, 1943, Commando, F1-Dream, GunSmoke, Tiger Road, Black Tiger, Bionic Commando, Higemaru, Street Fighter and Vulgus.
Stars: ✭ 65 (-20.73%)
Mutual labels:  verilog
Antikernel
The Antikernel operating system project
Stars: ✭ 75 (-8.54%)
Mutual labels:  verilog
Cdbus ip
CDBUS Protocol and the IP Core for FPGA users
Stars: ✭ 60 (-26.83%)
Mutual labels:  verilog
C65gs
FPGA-based C64 Accelerator / C65 like computer
Stars: ✭ 79 (-3.66%)
Mutual labels:  verilog
Practical Uvm Step By Step
This is the main repository for all the examples for the book Practical UVM
Stars: ✭ 56 (-31.71%)
Mutual labels:  verilog
Computerarchitecturelab
This repository is used to release the Labs of Computer Architecture Course from USTC
Stars: ✭ 75 (-8.54%)
Mutual labels:  verilog
Ponylink
A single-wire bi-directional chip-to-chip interface for FPGAs
Stars: ✭ 80 (-2.44%)
Mutual labels:  verilog
Homotopy
Homotopy theory in Coq.
Stars: ✭ 79 (-3.66%)
Mutual labels:  verilog
Minimig Aga mister
Stars: ✭ 77 (-6.1%)
Mutual labels:  verilog
View All Similar Projects ➔

Steps to install and run on UBUNTU:

  1. sudo apt-get install git
  2. git clone https://github.com/kunalg123/vsdflow.git
  3. cd vsdflow
  4. chmod 777 opensource_eda_tool_install.sh
  5. ./opensource_eda_tool_install.sh **NOTE for freshers : This has been tested on a fresh UBUNTU installtion **NOTE for experienced UNIX users : It has lot of sudo apt-get and sudo remove commands, so you might want to review before running
  6. ./vsdflow spi_slave_design_details.csv
  7. ./vsdflow picorv32_design_details.csv

Steps to install and run on CENTOS: First login as root using below command (IMPORTANT) su - Then follow below steps

  1. sudo yum install git
  2. git clone https://github.com/kunalg123/vsdflow.git
  3. cd vsdflow
  4. chmod 777 opensource_eda_tool_install_centos.sh
  5. sudo ./opensource_eda_tool_install_centos.sh **NOTE for freshers : This has been tested on a fresh CENTOS 7 installtion **NOTE for experienced UNIX users : It has lot of sudo yum commands, so you might want to review before running
  6. ./vsdflow spi_slave_design_details.csv
  7. ./vsdflow picorv32_design_details.csv

Steps to test 'vsdflow' on Ubuntu and CENTOS:

  1. cd outdir_spi_slave
  2. qflow display spi_slave

List of Tools installed:

  1. Yosys - RTL Synthesis
  2. blifFanout - High fanout net (HFN) synthesis
  3. graywolf - Placement
  4. qrouter - Detailed routing
  5. magic - VLSI Layout tool
  6. netgen - LVS
  7. OpenTimer and OpenSTA - Static timing analysis tool

'vsdflow' is also the best utility ever written for learning EDA based TCL scripting...Very hard to find a tool, with its detailed explanation in form of videos. 'vsdflow' is explained (in detail) in below 2 TCL scripting courses, so you might want to have a look:

TCL scripting part 1: https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert/

TCL scripting part 2: https://www.udemy.com/vsd-tcl-programming-from-novice-to-expert-part-2/

This course has gone to a level, where I have heard managers in VLSI industries asking their team to learn TCL only through this course and 'vsdflow'.

VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys).

The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, RISC-V picorv32, and can be further tested for multi-million instance count using hierarchical or glue logic.

Some background about VLSI backend is needed for to understand 'vsdflow' operations, so here are 3 important courses: (check with your interviewer and they might recommend these courses):

Physical design flow: https://www.udemy.com/vlsi-academy-physical-design-flow/

Static timing analysis - Part 1: https://www.udemy.com/vlsi-academy-sta-checks/

Static timing analysis - Part 2: https://www.udemy.com/vlsi-academy-sta-checks-2/

There you go...Write your first TCL script, learn it from basics to advanced to expert level, apply it from EDA perspective, and you are good to go for your job or interviews....

All the best and happy learning

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].