All Projects → mu-chaco → Rewire

mu-chaco / Rewire

Licence: other
Experimental compiler for a subset of Haskell to VHDL

Labels

Projects that are alternatives of or similar to Rewire

Parallella Hw
Parallella board design files
Stars: ✭ 389 (+3790%)
Mutual labels:  vhdl
Ece368 Lab
ECE368 | Lab
Stars: ✭ 6 (-40%)
Mutual labels:  vhdl
Floating point library Jhu
VHDL for basic floating-point operations.
Stars: ✭ 22 (+120%)
Mutual labels:  vhdl
Gplgpu
GPL v3 2D/3D graphics engine in verilog
Stars: ✭ 515 (+5050%)
Mutual labels:  vhdl
Ustc Tmips
Stars: ✭ 6 (-40%)
Mutual labels:  vhdl
Nexys4ddr
Stars: ✭ 16 (+60%)
Mutual labels:  vhdl
Awesome Hdl
Hardware Description Languages
Stars: ✭ 385 (+3750%)
Mutual labels:  vhdl
Nexyspsram
AXI PSRAM Controller IP for use with Digilent Nexys 4
Stars: ✭ 7 (-30%)
Mutual labels:  vhdl
Sha 256 Hdl
An implementation of original SHA-256 hash function in (RTL) VHDL
Stars: ✭ 6 (-40%)
Mutual labels:  vhdl
Audioxtreamer
ASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.
Stars: ✭ 22 (+120%)
Mutual labels:  vhdl
Spinalhdl
Scala based HDL
Stars: ✭ 696 (+6860%)
Mutual labels:  vhdl
Fpga webserver
A work-in-progress for what is to be a software-free web server for static content.
Stars: ✭ 762 (+7520%)
Mutual labels:  vhdl
Zedboard audio
A Audio Interface for the Zedboard
Stars: ✭ 16 (+60%)
Mutual labels:  vhdl
Vunit
VUnit is a unit testing framework for VHDL/SystemVerilog
Stars: ✭ 438 (+4280%)
Mutual labels:  vhdl
Openrio
Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
Stars: ✭ 23 (+130%)
Mutual labels:  vhdl
Gcvideo
GameCube Digital AV converter
Stars: ✭ 385 (+3750%)
Mutual labels:  vhdl
I2s Interface Vhdl
A simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.
Stars: ✭ 6 (-40%)
Mutual labels:  vhdl
Multicomp
Simple custom computer on a FPGA
Stars: ✭ 8 (-20%)
Mutual labels:  vhdl
Aes
AES-128 hardware implementation
Stars: ✭ 25 (+150%)
Mutual labels:  vhdl
Hashvoodoo Fpga Bitcoin Miner
HashVoodoo FPGA Bitcoin Miner
Stars: ✭ 16 (+60%)
Mutual labels:  vhdl

ReWire

Build Status

ReWire is an experimental compiler for a subset of Haskell to VHDL, suitable for synthesis and implementation on FPGAs. ReWire enables a semantics-directed style of synchronous hardware development, based on reactive resumption monads. See the online documentation for more information.

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].