magro732 / Openrio
Licence: lgpl-3.0
Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
Projects that are alternatives of or similar to Openrio
MicrowattA tiny Open POWER ISA softcore written in VHDL 2008
Stars: ✭ 383 (+1565.22%)
Mutual labels: vhdl
Cocotbcocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Stars: ✭ 740 (+3117.39%)
Mutual labels: vhdl
Nexys4ddr Stars: ✭ 16 (-30.43%)
Mutual labels: vhdl
Awesome HdlHardware Description Languages
Stars: ✭ 385 (+1573.91%)
Mutual labels: vhdl
GplgpuGPL v3 2D/3D graphics engine in verilog
Stars: ✭ 515 (+2139.13%)
Mutual labels: vhdl
Ustc Tmips Stars: ✭ 6 (-73.91%)
Mutual labels: vhdl
Mist BoardCore sources and tools for the MIST board
Stars: ✭ 350 (+1421.74%)
Mutual labels: vhdl
AudioxtreamerASIO driver, Usb Driver, FX2LP Firmware, VHDL Fpga, Schematics & PCB Layout for the AudioXtreamer, a USB 2.0 32ch Audio/Midi interface for retrofitting into digital mixers/interfaces.
Stars: ✭ 22 (-4.35%)
Mutual labels: vhdl
SpinalhdlScala based HDL
Stars: ✭ 696 (+2926.09%)
Mutual labels: vhdl
I2s Interface VhdlA simplified i2s interface taken from OpenCores' I2S Interface. Aimed for Altera Avalon Streaming interface.
Stars: ✭ 6 (-73.91%)
Mutual labels: vhdl
GcvideoGameCube Digital AV converter
Stars: ✭ 385 (+1573.91%)
Mutual labels: vhdl
VunitVUnit is a unit testing framework for VHDL/SystemVerilog
Stars: ✭ 438 (+1804.35%)
Mutual labels: vhdl
Sha 256 HdlAn implementation of original SHA-256 hash function in (RTL) VHDL
Stars: ✭ 6 (-73.91%)
Mutual labels: vhdl
Parallella ExamplesCommunity created parallella projects
Stars: ✭ 384 (+1569.57%)
Mutual labels: vhdl
Zedboard audioA Audio Interface for the Zedboard
Stars: ✭ 16 (-30.43%)
Mutual labels: vhdl
Riscv vhdlPortable RISC-V System-on-Chip implementation: RTL, debugger and simulators
Stars: ✭ 356 (+1447.83%)
Mutual labels: vhdl
Fpga webserverA work-in-progress for what is to be a software-free web server for static content.
Stars: ✭ 762 (+3213.04%)
Mutual labels: vhdl
Ece368 LabECE368 | Lab
Stars: ✭ 6 (-73.91%)
Mutual labels: vhdl
This project started when Bombardier Transportation Sweden decided to donate some RapidIO-IP blocks that were developed in an internal project. It was initialy hosed on http://opencores.org/project,rio but has now moved to GitHub to take advantage of all the Git features.
The cores that were initially commited were aiming to use RapidIO in proprietary systems with a legazy infrastructure and did not support the full standard PCS (Physical Coding Sublayer) implementation. It instead showed a way of building RapidIO fully compliant networks based on non-RapidIO compliant, low-speed, UART links. This shows that the RapidIO protocol is very flexible and can be scaled not only up in bandwidth but also down.
Since the initial releases an effort has started to write a fully compliant PCS layer.
Currently this project contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints. These three configuration can be acheived by changing how the IP-blocks in the project are interconnected.
Questions/comments can be sent to: magro732(at)hemmai.se
Note that the project description data, including the texts, logos, images, and/or trademarks,
for each open source project belongs to its rightful owner.
If you wish to add or remove any projects, please contact us at
[email protected].
