All Projects → luojia65 → Rustsbi

luojia65 / Rustsbi

Licence: other
RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

Programming Languages

rust
11053 projects

Labels

Projects that are alternatives of or similar to Rustsbi

Cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Stars: ✭ 458 (+231.88%)
Mutual labels:  riscv
Fpga101 Workshop
FPGA 101 - Workshop materials
Stars: ✭ 54 (-60.87%)
Mutual labels:  riscv
Homebrew Riscv
homebrew (macOS) packages for RISC-V toolchain
Stars: ✭ 105 (-23.91%)
Mutual labels:  riscv
Capstone
Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.
Stars: ✭ 5,374 (+3794.2%)
Mutual labels:  riscv
Darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
Stars: ✭ 1,062 (+669.57%)
Mutual labels:  riscv
Cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Stars: ✭ 1,144 (+728.99%)
Mutual labels:  riscv
Probe Rs
A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host
Stars: ✭ 435 (+215.22%)
Mutual labels:  riscv
Diosix
A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V
Stars: ✭ 116 (-15.94%)
Mutual labels:  riscv
Rocket Rocc Examples
Tests for example Rocket Custom Coprocessors
Stars: ✭ 52 (-62.32%)
Mutual labels:  riscv
Risc V article paper src
riscv资料、论文等
Stars: ✭ 89 (-35.51%)
Mutual labels:  riscv
Riscv Boom
SonicBOOM: The Berkeley Out-of-Order Machine
Stars: ✭ 852 (+517.39%)
Mutual labels:  riscv
Vexriscv
A FPGA friendly 32 bit RISC-V CPU implementation
Stars: ✭ 1,041 (+654.35%)
Mutual labels:  riscv
Ustc Rvsoc
FPGA-based RISC-V CPU+SoC.
Stars: ✭ 77 (-44.2%)
Mutual labels:  riscv
Rv8
RISC-V simulator for x86-64
Stars: ✭ 476 (+244.93%)
Mutual labels:  riscv
Neorv32
A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
Stars: ✭ 106 (-23.19%)
Mutual labels:  riscv
Unicorn
Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)
Stars: ✭ 4,934 (+3475.36%)
Mutual labels:  riscv
Riscy
Riscy Processors - Open-Sourced RISC-V Processors
Stars: ✭ 54 (-60.87%)
Mutual labels:  riscv
Rcore
Rust version of THU uCore OS. Linux compatible.
Stars: ✭ 2,175 (+1476.09%)
Mutual labels:  riscv
Meta Riscv
OpenEmbedded/Yocto layer for RISC-V Architecture
Stars: ✭ 114 (-17.39%)
Mutual labels:  riscv
Cores Swerv El2
SweRV EL2 Core
Stars: ✭ 79 (-42.75%)
Mutual labels:  riscv

RustSBI

RISC-V Supervisor Binary Interface (SBI) implementation in Rust; runs on M-mode.

crates.io Documentation License

Binary downloads

See releases.

Binaries are available for platforms which can be found on platform support page. This page includes an instruction to write your own RustSBI implementation on production use, and some reference implementations for experiments.

Features

  • Functional and extensible operating system runtime
  • Fully support to RISC-V SBI specification v0.2
  • Adapted for unix-like operating systems
  • Written in Rust
  • Competitive to OpenSBI with most of its function
  • Bundled with a test framework for SBI implementations
  • Supports QEMU emulator (priv. spec v1.11)
  • Backward compatible to Kendryte K210 with spec v1.9, MMU and S-Mode

Components

The RustSBI project contains three parts: the RustSBI library rustsbi, reference implementation in platform, and a simple operating system kernel to test SBI implementations in test-kernel.

The test kernel is used to test SBI functions. Boot this kernel using your platform, it will call all SBI calls and run instructions to test if underlying SBI environment is okay. if this kernel reports 'SUCCESS' and exits normally, it means that your SBI implementation is correct.

Talks and documents

This project is originally a part of rCore Summer of Code 2020 activities, now it is capable of running rCore-Tutorial and other OS kernels on wide supported RISC-V devices.

Blog article (Chinese):

Slides (Chinese):

Notes on platform implementation

  1. RustSBI can be used as a library. Under normal circumstances, RustSBI platform can be implemented with embedded Rust's embedded-hal libraries.
  2. On both QEMU and K210 platform, we supports CLINT and PLIC peripherals. Embedded Rust's community still need more SoCs taped out to discuss on common libraries on RISC-V ecosystem. After these works are done, we may use crates then to implement QEMU, without the hal module we have now.
  3. Contributions are welcomed! We welcome to implement RustSBI for both FPGA cores and real cores. Implementations for emulators are also welcomed. Fire a pull request if you are ready!

License & Copyright

This project is licensed under either of

This project contains documents from RISC-V SBI specification repository. These documents are (C) RISC-V community under CC-BY 4.0 license.

Note that the project description data, including the texts, logos, images, and/or trademarks, for each open source project belongs to its rightful owner. If you wish to add or remove any projects, please contact us at [email protected].