93 Open source projects that are alternatives of or similar to Rustsbi

Quasar 2.0: Chisel equivalent of SweRV-EL2

The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core

RARS -- RISC-V Assembler and Runtime Simulator

Project Migration tools to help you migrating to IAR Embedded Workbench more efficiently.

The Gee (寂) Operating System, written in YuLang.

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Interpreter experiment. Testing dispatch methods: Switching, Direct/Indirect Threaded Code, Tail-Calls and Inlining

FPGA 101 - Workshop materials

RISC-V SystemC-TLM simulator

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Maxine VM: A meta-circular research VM

Simple risc-v emulator, able to run linux, written in C.

Capstone disassembly/disassembler framework: Core (Arm, Arm64, BPF, EVM, M68K, M680X, MOS65xx, Mips, PPC, RISCV, Sparc, SystemZ, TMS320C64x, Web Assembly, X86, X86_64, XCore) + bindings.

支持CMSIS-DAP v2接口协议，支持ARM、RISCV、ESP32等目标芯片，详见Wiki及release

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Tutorial on how to build Docker Images for the IAR Build Tools on Linux hosts. The IAR Build Tools on Linux are available for Arm, RISC-V and Renesas (RH850, RL78 and RX).

A debugging toolset and library for debugging embedded ARM and RISC-V targets on a separate host

A kernel written in Rust

homebrew (macOS) packages for RISC-V toolchain

RISCV SoftCPU Contest 2018

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

ARV: Asynchronous RISC-V Go High-level Functional Model

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

RISC-V RV32I[MAC] emulator with ELF support

RISC-V Assembler and Runtime Simulator

A self-hosting and educational C compiler

pulp_soc is the core building component of PULP based SoCs

SonicBOOM: The Berkeley Out-of-Order Machine

RISC-V processor emulator written in Rust+WASM

FPGA-based RISC-V CPU+SoC.

Nuclei Microcontroller Software Interface Standard Development Repo

RISC-V simulator for x86-64

xv6-riscv like OS written in Rust

A small and customizable full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.

RISC-V Supervisor Binary Interface (RISC-V SBI) implementation in Rust; runs on M-mode; good support for embedded Rust ecosystem

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, X86)

C/Assembly macros for talking with Rocket Custom Coprocessors (RoCCs)

Riscy Processors - Open-Sourced RISC-V Processors

⛔ DEPRECATED ⛔ HERO Software Development Kit

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

Documentatin for YatCPU

A lightweight, secure, multiprocessor bare-metal hypervisor written in Rust for RISC-V

FreeBSD adapted for CHERI-RISC-V and Arm Morello.

SweRV EH1 core

An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

Tests for example Rocket Custom Coprocessors

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

A deep learning-powered visual navigation engine to enables autonomous navigation of pocket-size quadrotor - running on PULP

MDEPX — A BSD-style RTOS

riscv资料、论文等

The RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.

A 32-bit RISC-V / MIPS ISA retargetable CPU core & SoC, 1.63 DMIPS/MHz

FIPS and higher-level algorithm tests for RISC-V Crypto Extension

A FPGA friendly 32 bit RISC-V CPU implementation

Self-hosting metacompiled Forth, bootstrapping from a few lines of C; targets Linux, Windows, ARM, RISC-V, 68000, PDP-11, asm.js.

Rust version of THU uCore OS. Linux compatible.

OpenEmbedded/Yocto layer for RISC-V Architecture

SweRV EL2 Core

Rust's hardware abstract layer (HAL) for K210 chip, a dual RV64GC SoC with hardware accelerated AI peripherals. Contributions welcomed!

RISC-V emulator for CLI and Web written in Rust with WebAssembly. It supports xv6 and Linux (ongoing).