The lab schedules for EECS168 at UC Riverside

An open source library for image processing on FPGA.

Hardware Description Languages

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

The RIFFA development repository

Verilog AXI components for FPGA implementation

NetFPGA 1G infrastructure and gateware

A Just-In-Time Compiler for Verilog from VMware Research

mor1kx - an OpenRISC 1000 processor IP core

A tiny Open POWER ISA softcore written in VHDL 2008

Repository for basic (and not so basic) Verilog blocks with high re-use potential

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

SERV - The SErial RISC-V CPU

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

The OpenPiton Platform

RISC-V Formal Verification Framework

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

MIPS CPU implemented in Verilog

🌱 Open source ecosystem for open FPGA boards