342 Open source projects that are alternatives of or similar to Sd2snes

A collection of phase locked loop (PLL) related projects

List of ideas for getting started with TimVideos projects

RISC-V CPU Core (RV32IM)

An FPGA implementation of a classic 80ies speech synthesizer. Done for the Retro Challenge 2017/10.

A configurable C++ generator of pipelined Verilog FFT cores

The lab schedules for EECS168 at UC Riverside

Global Dark Mode for ALL apps on ANY platforms.

An open source library for image processing on FPGA.

Wishbone controlled I2C controllers

An abstraction library for interfacing EDA tools

Chisel Things for OFDM

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

OpenLANE is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

Scripts to build and use docker images including GHDL

Verilog AXI components for FPGA implementation

C++17 implementation of an AST for Verilog code generation

NetFPGA 1G infrastructure and gateware

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Hardware Description Languages

FPGA core for SHA256d mining targeting Lattice iCE40 devices.

Documenting the Lattice ECP5 bit-stream format.

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, Fault and custom methodology scripts for design exploration and optimization.

The RIFFA development repository

Project Oberon (New Edition 2013) Unofficial Mirror

Imitate SDcard using FPGAs.

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 7…

A full-speed device-side USB peripheral core written in Verilog.

Repository for basic (and not so basic) Verilog blocks with high re-use potential

Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source language - VHDL / Verilog). GNU GPL 3.0.

SERV - The SErial RISC-V CPU

Homebrew game for homebrew FPGA game console

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

Video Game custom chips reverse-engineered from silicon

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

Robotic Application Processor

The OpenPiton Platform

FPGA-based USB-device controller to implement USB-CDC, USB-HID, etc.

RISC-V Formal Verification Framework

Minimal SDR with Lattice MachXO2 FPGA. And a port to Cyclone3 by Steven Groom

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

ZX Spectrum CPLD-based clone for rubber case

A Just-In-Time Compiler for Verilog from VMware Research

Efficient implementations of the transcendental functions

OpenROAD's unified application implementing an RTL-to-GDS Flow

Useful m-scripts for DSP (CIC, FIR, FFT, Fast convolution, Partial Filters etc.)

mor1kx - an OpenRISC 1000 processor IP core

Verilog Language Extension for Visual Studio

Various HDL (Verilog) IP Cores

This repo contains code snippets written in verilog as part of course Computer Architecture of my university curriculum

A tiny Open POWER ISA softcore written in VHDL 2008

Ruby interface to IEEE 1364-2005 Verilog VPI

Verilog PCI express components

Verilog grammar for tree-sitter

FPGA Haskell machine with game changing performance. Reduceron is Matthew Naylor, Colin Runciman and Jason Reich's high performance FPGA softcore for running lazy functional programs, including hardware garbage collection. Reduceron has been implemented on various FPGAs with clock frequency ranging from 60 to 150 MHz depending on the FPGA. A high degree of parallelism allows Reduceron to implement graph evaluation very efficiently. This fork aims to continue development on this, with a view to practical applications. Comments, questions, etc are welcome.

Test suite designed to check compliance with the SystemVerilog standard.

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

MIPS CPU implemented in Verilog

🌱 Open source ecosystem for open FPGA boards

KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS

Haskell library for hardware description