yatcpuYet another toy CPU.
Stars: ✭ 42 (+180%)
Mutual labels: riscv, chisel3
tree-core-ideThe next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
Stars: ✭ 79 (+426.67%)
Mutual labels: riscv, chisel3
QuasarQuasar 2.0: Chisel equivalent of SweRV-EL2
Stars: ✭ 19 (+26.67%)
Mutual labels: riscv, chisel3
KyogenRVThe Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
Stars: ✭ 37 (+146.67%)
Mutual labels: riscv, chisel3
GeeOSThe Gee (寂) Operating System, written in YuLang.
Stars: ✭ 22 (+46.67%)
Mutual labels: riscv
ravelA RISC-V simulator
Stars: ✭ 24 (+60%)
Mutual labels: riscv
fedar-f1-rv64im5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.
Stars: ✭ 131 (+773.33%)
Mutual labels: riscv
tornado-os异步内核就像风一样快!
Stars: ✭ 264 (+1660%)
Mutual labels: riscv
cheribsdFreeBSD adapted for CHERI-RISC-V and Arm Morello.
Stars: ✭ 95 (+533.33%)
Mutual labels: riscv
RISC-V-TLMRISC-V SystemC-TLM simulator
Stars: ✭ 125 (+733.33%)
Mutual labels: riscv
rv32emuRISC-V RV32I[MAC] emulator with ELF support
Stars: ✭ 61 (+306.67%)
Mutual labels: riscv
sednaSedna - a pure Java RISC-V emulator.
Stars: ✭ 52 (+246.67%)
Mutual labels: riscv
mdepxMDEPX — A BSD-style RTOS
Stars: ✭ 17 (+13.33%)
Mutual labels: riscv
yarviYet Another RISC-V Implementation
Stars: ✭ 59 (+293.33%)
Mutual labels: riscv
T13xAn Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP
Stars: ✭ 28 (+86.67%)
Mutual labels: riscv
RiscvSpecFormalThe RiscvSpecKami package provides SiFive's RISC-V processor model. Built using Coq, this processor model can be used for simulation, model checking, and semantics analysis. The RISC-V processor model can be output as Verilog and simulated/synthesized using standard Verilog tools.
Stars: ✭ 69 (+360%)
Mutual labels: riscv
rvkrypto-fipsFIPS and higher-level algorithm tests for RISC-V Crypto Extension
Stars: ✭ 18 (+20%)
Mutual labels: riscv
FuxiFuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
Stars: ✭ 68 (+353.33%)
Mutual labels: riscv
riscv emSimple risc-v emulator, able to run linux, written in C.
Stars: ✭ 51 (+240%)
Mutual labels: riscv
araThe PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
Stars: ✭ 116 (+673.33%)
Mutual labels: riscv